A 4.7-ps Resolution Recirculating Cyclic Vernier TDC Using DWA-Based Mismatch Correction and a Register-Based Time Amplifier

Abstract

Herein, we present a recirculating (RC) cyclic Vernier time-to-digital converter (TDC) using dynamic element matching and a register-based time amplifier (TA). The RC TDC reuses a single conversion stage for multiple conversions that are suitable for low power and compact realization. Good matching is achieved between multiple conversions because the same stage is reused. Processing the amplified residue further enhances the TDC resolution. We propose a new TA based on a time register that achieves a well-controlled time magnification over a wide input range. Unlike conventional approaches based on regeneration or meta-stability, the register-based TA does not suffer from a narrow input range. The proposed TA achieves a relatively high gain accuracy (< 1.5%) over a wide input range from 40 to 400 ps. Compact TDC implementation is further facilitated using the multiphase operation of a gated ring oscillator (GRO) in a cyclic Vernier structure. Using the phase-preserving characteristic of the GRO, the mismatch is first order shaped by data weight averaging. The RC TDC fabricated using a 28-nm CMOS process is realized in a small area of 0.0096 mm2. Measurements show that the TDC can be successfully configured into four gain modes with a resolution of 11.5, 7.7, 5.8, and 4.7 ps in a 12-bit dynamic range. The full range linearity measurement shows an integral nonlinearity of less than 1.48 LSB. The power consumption is 0.188 mW at a conversion rate of 3.51 MHz, leading to a favorable figure of merit of 0.032 pJ/conv.-step. The results show the effectiveness of the RC structure in realizing a high-performance, compact TDC.