A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL

Abstract

This paper presents a novel Time-to-digital converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a gated ring oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. The proposed TDC is designed in 90 nm CMOS process. Simulation results show that the TDC achieves a large detectable conversion range that extends between 0.285 and 10 ns. The attained time resolution is 9.4 ps, which corresponds to half the delay time of an inverter. The TDC is self-calibrating with estimated accuracy better than 0.28%. The structure consumes 6.6 mA current from a 1.0 V voltage supply, when operating at a clock frequency of 13 MSPS. The estimated differential nonlinearity and integral nonlinearity are ±0.48 LSB and ±0.6 LSB respectively. Compared to previously reported TDC, this implementation achieves a competitive FoMP without requiring complicate calibration.