An 8.5-ps Two-Stage Vernier Delay-Line Loop Shrinking Time-to-Digital Converter in 130-nm Flash FPGA

Abstract

A new time-to-digital converter (TDC) with high resolution and high precision is designed and tested in this paper. The converter is realized by combining coarse clock counter with a two-stage delay-line loop shrinking interpolator (DLLSI) based on Vernier configuration, and its prototype has been implemented in a low-cost flash field-programmable gate array device SmartFusion A2F200M3F (Actel). Delay-line loops are used to achieve differential Vernier delay unit and directly shrink the time interval. In order to improve the resolution, decrease measurement time, and diminish the jitter of the cyclic pulse, a two-stage DLLSI method is proposed. The first-stage interpolator rapidly shrinks the measured time interval with low resolution, and the second-stage interpolator determines the final fine resolution. The resolutions are dependent on the entire delay time differences between two delay-line loops of each interpolator. The optimal resolutions are theoretically calculated, and statistic code density test is used to estimate the resolution of the implemented TDC. The implemented two-stage DLLSI has achieved 8.5-ps resolution with 42.4-ps standard deviation and 10-ns dynamic range. The maximum integral and differential nonlinearity errors are less than 7.8 and 3.1 ps.