Abstract
ABSTRACTIn this paper, a novel pipeline time-to-digital converter (TDC) is presented which employs dual-slope analog interpolation and time amplification techniques for digitizing the time interval between two input signals. The proposed converter will be a 9-bit pipeline TDC which contains three 2.5 b/stage TDCs based on analog interpolation and a delay line TDC stage. The proposed converter features low circuit complexity, low sensitivity to temperature, power supply and process (PVT) variations, and high accuracy compared with the TDCs that have previously been proposed. This converter improves the resolution and the dynamic range. Also, the converter reduces the active chip area, the power consumption, and the figure of merit. In addition, the integral nonlinearity and differential nonlinearity errors are improved. In order to evaluate the idea, the proposed TDC is designed in TSMC 0.18μm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.
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