Abstract
This paper investigates a novel cyclic time-to- digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digi- tizing the time interval between the rising edges of two input signals (Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitiv- ity to temperature, power supply and process (PVT) varia- tions. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. This converter also improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC re- duces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM). In this converter, the inte- gral nonlinearity (INL) and differential nonlinearity (DNL) errors are reduced. In order to evaluate the idea, the pro- posed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theo- retical and simulation results confirms the benefits of the proposed TDC.
Highlights
High resolution time-to-digital converter (TDC) has been widely used in many applications such as on-chip time signal measurement systems, biochemical sensor readouts and frequency synthesis circuits [1], All Digital Phase Locked Loops (ADPLLs) [2], [3], laser range finders [4], digital storage oscilloscopes, and capacitive sensor readouts [5]
This paper investigates a novel cyclic TDC that employs analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals as well as increasing the resolution
The simulation results of the proposed 9-bit cyclic TDC are investigated
Summary
High resolution time-to-digital converter (TDC) has been widely used in many applications such as on-chip time signal measurement systems, biochemical sensor readouts and frequency synthesis circuits [1], All Digital Phase Locked Loops (ADPLLs) [2], [3], laser range finders [4], digital storage oscilloscopes, and capacitive sensor readouts [5]. Direct conversion TDCs employ delay-line elements which include a chain of buffers or inverters in their structure These converters are used to measure short time intervals between the rising edges of the input signals [7], [8]. The main disadvantages of direct conversion TDCs are the circuit complexity, which results in high power consumption and high sensitivity to PVT variations [9]. These converters are sensitive to the mismatch between the elements causing the non-linear factors. Indirect conversion TDCs feature low sensitivity to PVT variation, sub-gate resolution, simple circuit structure, low chip area, and good dynamic range.
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