Time-interleaved ADC Research Articles

Low computing resource consumption fully digital foreground calibration technique for time-interleaved analog-to-digital converter

A time-interleaved analog-to-digital converter (TI-ADC) uses several sub-analog-to-digital converters (sub-ADCs) to achieve a high sampling rate. Its applications include communication systems, oscilloscopes, healthcare instruments, etc. However, the presence of sub-ADC channel mismatches such as offset, gain and sample-time mismatches can significantly degrade the performance of TI-ADCs. This paper proposes a fully digital foreground calibration technique for the TI-ADC, including mismatch correction and estimation blocks. Unlike existing techniques, the proposed technique requires low computational resources. As the resource for complex computing in a field-programmable gate array (FPGA) is mainly the digital signal processor (DSP), the mismatch correction block unifies each computing unit in the FPGA into a multiply adder to achieve low DSP consumption. To further reduce the use of DSP resources, the selection of an optimal number of taps of the finite impulse response filter used for mismatch correction is discussed. The optimal-tap filter that uses the lowest amount of DSPs while satisfying the required signal-to-noise and distortion ratio flat area bandwidth is presented. A real-time hardware correction block was implemented for an 8 Gs/s TI-ADC system with two sub-ADC channels, and the results with this hardware verify the low computing resource consumption feature of the proposed calibration technique.

An Improved All-Digital Background Calibration Technique for Channel Mismatches in High Speed Time-Interleaved Analog-to-Digital Converters

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.

A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

This letter describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dual-comparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.

A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications

This article presents a 16-channel 5 GS/s time-interleaved (TI) SAR ADC for a direct-sampling receiver that employs a digital-mixing background timing mismatch calibration to compensate for timing-skew errors. It uses a first-order approximation to obtain the derivative of the autocorrelation of the input signal, subsequently used to evaluate the explicit amount of the timing-skew. Therefore, this allows a digital background calibration of the timing-skew, avoiding extra analog circuits. The proposed 16-channel TI ADC uses a splitting-combined monotonic DAC switching method for the individual SAR channel to achieve a trade-off of simple switching and small common-mode voltage variation of the comparator. The prototype, implemented in 28 nm CMOS, reaches a 48.5/47.8 dB SNDR with an input signal of 2.38/4.0 GHz after the proposed background timing mismatch calibration, respectively. Furthermore, the ADC core’s power consumption is 29 mW sampling at 5 GS/s, with a Walden FoM of 26.7 fJ/conv.-step and a Schreier FoM of 157.9 dB.

A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs

This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can provide an improvement in the SFDR without incurring a penalty in the SNDR. The calibration algorithm places some constraints on the random sampling sequence, which are satisfied via a proposed sequence generation algorithm based on a linear-feedback shift register (LFSR). We also show how the timing reference can be selected so as to reduce the requirements of the time-skew correction circuit, and we demonstrate the resulting production yield improvements. The proposed algorithm was synthesized for a TIADC composed of 9 sub-ADCs having an aggregated sampling rate of 2.4GS/sec in a 28nm process; the design occupies 0.014mm2 and consumes 2.93mW. We demonstrate that the proposed algorithm successfully compensates the time-skew mismatch, allowing to achieve SFDR above 100dB.

A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC

This paper presents a split-based feedforward calibration technique for timing mismatch of Time-Interleaved Analog-to-Digital Converter (TI-ADC). The timing mismatch is estimated by using the difference between corresponding sample points of paired split-sub-ADCs, and compensated by a non-derivative interpolation method. Compared with traditional feedback methods with LMS iterative, the proposed feedforward calibration method can achieve much higher calibration speed and the complexity of digital post-processing is greatly relaxed without using of any dummy channel or filters. In addition, it has good calibration effects in both single-tone and multi-tone input conditions. Applied in a 1 GS/s 12-bit TIADC, the simulation result shows a convergence time of 1 × 104Ts under Nyquist frequency input with 2%Ts initial timing mismatch, and the peak signal to noise and distortion ratio of TI-ADC is improved from 37.54 dB to 67.60 dB with a normalized frequency of single-tone input signal fin/fS = 0.474. For a multi-tone input signal which contains 10 evenly distributed frequency points in the Nyquist frequency range, after calibration, the signal to noise and distortion improves 28.33 dB.

All-digital background calibration of gain and timing mismatches in time-interleaved ADCs using adaptive noise canceller

This paper proposes a novel all-digital background calibration technique for gain and timing mismatches in Time-Interleaved Analog-to-Digital Converters (TIADCs) using adaptive noise canceller (ANC). The error signals due to the gain and timing mismatches are expressed in linear regression terms, producing the estimation problem of ANC. The gain and clock skew coefficients are estimated by maximizing the output signal-to-noise ratio in ANC system. The correction is simple by subtracting the re-constructed errors from the TIADC output. The proposed calibration technique eliminates the input spectrum constants as well as removes high-pass filters, which are required in the conventional free-band based calibration technique. In order to validate the proposed approach, simulations are carried out for an 11-bit, 2.7GS/s four-channel TIADC for various input signals. Results show that the proposed calibration produces excellent performance in terms of mismatch distortion suppression. It achieves the SNDR and SFDR improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation on Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36% of the hardware resources of the FPGA chip and reduces the mismatch tone level up to -87dB.

A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4,000 Conversions/Channel

Split analog-to-digital converter (ADC) digital background calibration with full-input-range error detection schemes is proposed to rapidly correct the gain and nonlinearity errors in the multi-bit first stage of a multi-channel time-interleaved (TI) pipelined ADC. By adding a vertical shift between the residue transfer curves of the first stages in two half-ADCs which are split from a single ADC, the error detection schemes of the proposed calibration are effective in the full-input range. The larger error detection range means that calibration is activated more often, resulting in fewer ADC conversions to converge. In addition, the designed fast-settling switch controller enables a 12-bit resistor-ladder DAC (R-DAC) for high-speed application. Furthermore, by applying the proposed calibration and sharing the R-DAC among all channels, the need for gain mismatch calibration between interleaved channels is eliminated. Consequently, the calibration time and complexity are further reduced. A 12-bit 400-MS/s 4-channel TI pipelined ADC prototype is implemented in 40-nm CMOS technology with an active area of 0.71 mm2, the measured SNDR and INL of which are improved up to 23 dB and 96 LSB via the proposed calibration. Compared with prior-art ADCs using background calibration, the proposed ADC achieves the fastest background calibration in 4,000 conversions/channel, which is at least $5{\times }$ less than the others.

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs

This paper presents an all-digital background calibration technique for the time skew mismatch in time-interleaved ADCs (TIADCs). The technique jointly estimates all of the time skew values by processing the outputs of a bank of correlators. A low-complexity sampling sequence intervention technique, suitable for successive approximation register (SAR) ADC architectures, is proposed to overcome the limitations associated with blind estimation. A two-stage digital correction mechanism based on the Taylor series is proposed to satisfy the target high-precision correction. A quantitative study is performed regarding the requirements imposed on the digital correction circuit in order to satisfy the target performance and yield, and a corresponding filter design method is proposed, which is tailored to meet these requirements. Mitchell’s logarithmic multiplier is adopted for the implementation of the principal multipliers in both the estimation and correction mechanisms, leading to a 25% area and power reduction in the estimation circuit. The proposed calibration is synthesized using a TSMC 28-nm HPL process targeting a 2.4-GHz sampling frequency for an eight-sub-ADC system. The calibration block occupies 0.03 mm2 and consumes 11 mW. The algorithm maintains the SNDR above 65 dB for a sinusoidal input within the target bandwidth.

Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs

In this brief, a novel scheme for the derivation of triple errors associated with Time-Interleaved Analog-to-Digital Converters (TI-ADCs) has been presented. This algorithm relies on the utilization of reference Analog-to-Digital Converter (ADC) for the background calibration process. The main advantage of the proposed architecture is that it provides the possibility to calibrate offset, gain and timing skew by utilization of a simple structure. The objective has been accomplished by adjusting the corresponding coefficients of each error. At first, the main idea has been introduced by mathematical expressions. Then, the architecture for extraction of each error has been derived from the calculations, and the generalized scheme has been demonstrated which extracts the errors. Finally, system-level simulations were provided to indicate the correct behavior of the proposed algorithm for a 12-bit 4-channel TI-ADC. Based on simulation results, the maximum value of 81dB for SFDR after calibration process has been achieved when an average error of 11ps was considered for each channel at the sampling frequency of 8GHz and 1GHz single tone input frequency. Also, the corresponding maximum value for SNDR is 66dB.

An 8-bit 10-GHz 21-mW Time-Interleaved SAR ADC With Grouped DAC Capacitors and Dual-Path Bootstrapped Switch

An 8-bit 10-GHz 8× time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path bootstrapped switch decouples critical signal from nonlinear capacitance to boost the sampling SFDR by more than 5 dB. The ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding an FoM of 37 fJ/conv.-step, the lowest among the reported ADCs with similar speeds and resolutions and more than 2× improvement from the state-of-the-art.

Novel adaptive blind calibration technique of time‐skew mismatches for any channel time‐interleaved analogue‐to‐digital converters

This article presented a novel digital blind calibration technique of time-skew mismatches for time-interleaved analogue-to-digital converter (TI-ADC). Based on the frequency-shifted and derived operation, the spurious signals could be reconstructed and subtracted from the sampled signal adaptively. The main advantage of the proposed calibration technique is applicable to any channel TI-ADC and could achieve higher performance in comparison with the state-of-the-arts. Numerical simulations and experimental results have demonstrated that the proposed calibration technique could significantly improve the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the TI-ADC system.

A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration

This paper presents a mean absolute deviation (MAD)-based background timing-skew calibration technique for time-interleaved (TI) ADCs. It uses a single comparator-based window detector to select input samples near the zero crossing and computes their MAD value, which is used as an indicator for the timing skew. The proposed technique has low computation complexity, as it only requires taking absolute value and averaging. It also has a fast convergence speed when operating in the background with unknown random inputs, as the MAD value can be accurately estimated with a small number of samples. A prototype 10-bit 2-way TI-SAR ADC is built in 40-nm CMOS to verify the proposed technique. It achieves over 52 dB of SNDR over the entire Nyquist band. Operating at 600 MS/s, it consumes 4.7 mW, which translates to a Walden figure-of-merit of 24-fJ/conversion-step.

A digital-mixing-based method for timing skew estimation in time-interleaved ADCs

Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs). Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward, however, calibration for timing-skew is still in a state of exploration. An efficient digital-mixing-based method to estimate timing skew in time-interleaved analog-to-digital converters (TI-ADCs) is proposed and verified. The timing skew can be estimated by digital-mixing and inverse sine function processing. The proposed method can greatly alleviate the effects of phase ambiguity. It is also insensitive to offset mismatch. A four-channel TI-ADC behavioral system of 10-bits 2 GS/s has been simulated to verify the performance of the method. Simulation results demonstrate that the method greatly improves the TI-ADC′s performance and is effective up to the severe timing skew mismatch.

A Full-Band Timing Mismatch Calibration Technique in Time-Interleaved ADCs

This paper proposes a full-band calibration scheme of timing mismatch for Time-Interleaved Analog-to-Digital Converters (TI-ADC) based on Automatic Identification (AI) detection scheme. Besides estimating the value of timing mismatch, AI detection scheme also judges the odd–even property of the Nyquist zone (NZ) which the input signal belongs to and thus adaptively adjusts the calibration polarity for full-band application. On the other hand, Successive-Approximation-Register (SAR) correction technique is employed to speed up the convergence process of calibration with low cost. The efficiency of the proposed calibration scheme is verified by MATLAB simulation and implementation on PCB. Both results show that with an input signal whose bandwidth is within any NZ, the proposed calibration methodology is effective. Compared with the traditional calibration schemes, the proposed calibration method achieves fast convergence speed with [Formula: see text] samples and costs less hardware with 2.1[Formula: see text]k gate counts.

Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers

Time-interleaving analog-to-digital converters (ADCs) decrease the required sampling rate for one ADC to achieve giga samples per second (GS/s) rates. The gain and timing mismatches among the ADCs generate aliasing signals, degrading the spurious-free dynamic range of the time-interleaved ADC (TI-ADC). The conventional digital correction methods for TI-ADCs have not considered an application to direct-radio-frequency (RF) sampling receivers. We present a digital correction method for bandpass sampling four-channel TI-ADCs in the receivers. The proposed method, based on a correction method for two-channel TI-ADCs, reduces the in-band aliasing signals of the four-channel TI-ADCs by using in-phase/quadrature-phase (I/Q) downconversion mixers, cascaded integrator-comb (CIC) filters, and automatic gain control (AGC) in the receiver. This allows the correction circuit including mismatch estimation to have fewer building blocks than the conventional methods: seven adders, seven multipliers, and no finite-impulse-response filters. Simulations and measurements show that the proposed method reduces the aliasing signals of 1.2 GS/s 12-bit four-channel TI-ADCs to less than −80 dBFS.

Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The digital delay is based on a Parallel Farrow Filter. Such architecture allows to reach a very high processing rate with wideband signals and it is suitable to be used with Time-Interleaved Analog to Digital Converters (TI-ADC). The proposed delay has been simulated in MATLAB, implemented on FPGA and characterized in terms of amplitude and phase response, maximum clock frequency and area.

Online digital offset mismatch compensation for high-speed time-interleaved ADC in real-time optical OFDM receiver.

The time-interleaved analog-to-digital converter (TI-ADC) is a good option to realize high-speed data conversion for both single-carrier and multi-carrier optical communication systems. Offset mismatch is one of its drawbacks, which causes distortion in the sampled data and degrades the bit error rate (BER) performance of communication systems. In this article, a low-complexity online digital offset mismatch compensation (OMC) scheme based on time-domain averaging is proposed and implemented with a commercial off-the-shelf field programmable gate array (FPGA) chip for high-speed optical OFDM communications. The proposed OMC scheme is experimentally demonstrated in real-time direct-detection optical OFDM receiver with a 5 GS/s TI-ADC. The experimental results show that the BER performance can be improved by more than an order of magnitude, by using the proposed OMC scheme, for both 16- and 64-QAM modulation formats. The receiver sensitivity can be improved by more than 5-dB in terms of the received optical power at the BER of 1e-3. What's more, the real-time measured BER performance is similar to that of by using offline DSP approaches and has good stability during the measurement period. Numerical simulations are performed under additive white Gaussian noise (AWGN) channel to fully verify the performance of the OMC scheme. It exhibits that the error floor in BER performance can be eliminated by using the OMC scheme and a negligible signal-to-noise ratio (SNR) penalty can be achieved compared with that of offset mismatch-free case.