Time-interleaved ADC Research Articles

Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.

An Enhanced Photonic-Assisted Sampling Approach for Spectrum-Sparse Signal by Compressed Sensing

Spectrum-sparse signals are vital for wideband radars and wireless communication applications. A high-speed analog-to-digital converter (ADC) with the capacities of tens of gigahertz sampling rates is often required to acquire these signals. In this work, an enhanced photonic-assisted sampling approach with the combination of the photonic-assisted time-interleaved ADC and compressed sensing techniques is presented, which enables the measured signal to be reconstructed through very few samples by utilizing the sparsity of the spectrum-spare signal. An ultrahigh spectral resolution Fourier dictionary is introduced to suppress the spectrum leakage and obtain the actual sparse expression of the spectrum-sparse signals. Moreover, a layered tracking orthogonal matching pursuit signal recovery algorithm is employed to reduce computational complexity and enhance processing speed. The performance of the proposed approach has been investigated via simulations and laboratory experiments by varying the applied spectrum-sparse signals over 100 times. The experimental result demonstrated that the proposed approach can capture the blind-frequency spectrum-sparse signal at the equivalent sampling rate of 1 GS/s by utilizing four parallel ADCs with a sampling rate of 50 MS/s. It is proven that the proposed approach achieves ~5 times higher equivalent sampling rate than the conventional PTIADC at the same sampling rate. This work provides a useful method for the acquisition of spectrum sparse signals in practical applications.

A Background M-Channel Time-Interleaved ADC Calibration for Multilevel Modulations Based on the Probability Density Function Difference and a Greedy Algorithm

This paper presents the first time-interleaved analog-to-digital background calibration targeted for multilevel modulations that can calibrate offset, gain, time skew and bandwidth mismatches (to the author&#x0027;s knowledge). The mismatch errors are estimated based on the interleaving channels histograms. Moreover, the proposed calibration can be adapted to any interleaving factor with a multiplication-less estimation logic based on a greedy algorithm. Numerical simulations show satisfactory performance improvements for a 2-level, a 4-level and an 8-level symbol transmission, along with 4-channel and 32-channel TI-ADC interleaving orders. Furthermore, a new SNDR formula is derived considering all the TI-ADC mismatch distortions that can be compared with the obtained results. The measurement results show the proposed calibration working under a binary PRBS31 pattern with both a 3.6 GS/s and 7.2 GS/s signaling rates for a 3.6 GS/s 2-channel TI-ADC experimental board.

On the Compensation of Timing Mismatch in Two-Channel Time-Interleaved ADCs: Strategies and a Novel Parallel Compensation Structure

On the Compensation of Timing Mismatch in Two-Channel Time-Interleaved ADCs: Strategies and a Novel Parallel Compensation Structure

Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs.

The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoMw of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

Time-interleaved Noise-shaping SAR ADC based on CIFF Architecture with Redundancy Error Correction Technique

A time-interleaved noise-shaping (TINS) successive approximation register (SAR) analog-to-digital converter (ADC) based on the cascade of integrators with feed-forward (CIFF) architecture can achieve a high resolution and wide bandwidth with a high energy efficiency. Because it does not use the summation pre-amplifier, the energy efficiency obtained using the proposed ADC is higher than that of the TINS-SAR ADC based on the error-feedback (EF) architecture. In addition, the proposed ADC uses only one final residue sampling capacitor, and thus, the complexity of the circuit is reduced. The proposed ADC is implemented in a 65-nm CMOS process. According to the post-layout simulation result, a signal to noise and distortion ratio (SNDR) of 69.2 dB can be obtained for a sampling rate of 800 MS/s and bandwidth of 100 MHz with a high energy efficiency.

Effective extraction method for triple errors in foreground calibration of TI‐ADCs

AbstractThis paper presents a novel procedure for detecting offset, gain, and timing skew errors in foreground calibration of time‐interleaved analog‐to‐digital converters (TI‐ADCs). An efficient peak detection scheme has been introduced, which is successfully employed to extract timing skew error. The designed method has also been extended to derive the gain and offset errors separately to form the generalized architecture. The objective is performed with the adjustment of the rational coefficient for each error. Simplicity and low hardware consumption will constitute the notable advantages of the proposed algorithm. Mathematical expressions have been provided to explain the principles. A special case in which all triple errors could exist together has also been analyzed. Then, the proposed architecture was implemented at the system level. Finally, the behavioral simulation results for a 12‐bit four‐channel TI‐ADC have been demonstrated to confirm the accuracy of the proposed algorithm. The simulation environment has consisted of the sampling frequency of 8 GHz for TI‐ADC and 1 GHz single‐tone input frequency for each channel (associated with the Gaussian noise). Based on the results, the maximum value of 77.21 dB for SFDR has been achieved after the calibration process when the average error of 9% for timing skew and 6% tolerance for gain were considered for the channels of TI‐ADC.

A Novel Time Delay Estimation and Calibration Method of TI-ADC Based on a Coherent Optical Communication System

In optical communication systems, coherent detection is a standard method. The received signal enters the digital domain after passing through a time-interleaved analog-to-digital converter (TI-ADC). However, the time delay of the ADC brings noise into the signal, which decreases the signal quality; therefore, ADC calibration is essential. At present, there are many calibration methods for time delay, but their performances are not satisfactory at a high sampling frequency. This paper presents a method of time delay estimation and calibration in a coherent optical communication system. First, the expected maximum (EM) method is used to roughly estimate the time delay and then transfer the estimated value into the trained back propagation (BP) neural network to generate more accurate results. Second, the sampled signal is reconstructed, and then a finite impulse response (FIR) filter is designed to compensate for the time delay. There are several advantages of the proposed method compared with previous works: the convergence with a BP network is faster, the estimation accuracy is higher, and the calibration does not affect the sample operation of the ADC working in the background mode. In addition, the proposed calibration method does not need additional circuits and its low power consumption provides more sources for dispersion compensation, error correction, and other subsequent operations in the coherent optical communication system. Based on the quadrature phase shift keying (QPSK) system, the proposed method was implemented in a 16-channel/8-bit, 40-GS/s ADC. After estimation and calibration, the relative error of estimation was below 1%, the signal noise distortion rate (SNDR) reached 55.9 dB, the spurious free dynamic range (SFDR) improved to 61.2 dB, and the effective number of bits (ENOB) was 6.7 bits. The results demonstrate that the proposed method has a better calibration performance than other methods.

Broadband Mismatch Calibration for Time-Interleaved ADC Based on Linear Frequency Modulated Signal

Time-interleaved analog-to-digital converters can significantly increase system sampling rate, but channel mismatches, such as gain mismatch, offset mismatch and phase mismatch, can cause great error in the system. The problem of broadband mismatches calibration for multichannel time-interleaved analog-to-digital converters system will be discussed in this paper by using the foreground calibration technique. Essentially, the calibration can be divided into two steps: First, all the mismatches between analog input and digital output will be measured by taking a linear frequency modulated signal as the reference signal; Next, a set of finite-impulse response filters will be calculated based on those mismatches to generate frequency dependent mismatches compensation, so that the signal to noise and distortion ratio, and spurious-free dynamic range will not be limited by the channel mismatches. There are two advantages of the proposed method when compared with previous methods. The complexity of error estimation can be reduced dramatically and high precision error estimation can also be achieved. In order to evaluate the performance, a series of experiments were conducted in a two-channel time-interleaved analog-to-digital converter system. The results show that the spurious-free dynamic range is improved by more than 10dB.

A Timing Mismatch Background Calibration Algorithm With Improved Accuracy

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

Frequency response mismatch calibration in 2-channel time-interleaved oscilloscopes.

The time-interleaved (TI) structure has been widely implemented in high speed, wideband data acquisition systems to increase the system sampling rate. However, the frequency responses of each sub-sampling path are not identical. This is named frequency response mismatches (FRMs). In TI-based printed circuit board level systems, due to the impact of the parasitic parameters, the FRMs are more complicated than the mismatches in TI analog-to-digital converters (TIADCs), which degrade the system performance severely. Therefore, the FRM calibration in 2-channel TI acquisition systems with two features is researched. The first one is that the TI system has a larger mismatch range than in most previous research. The second one is that the channel frequency response uses the general model. The calibration structure is established by the analysis of the digital TI model, which implements the TI operation in the digital domain to reconstruct the mismatches in the time domain. Furthermore, the problem of designing an arbitrary frequency response filter is transformed to the question of designing a three-stage cascaded filter group, which gives a method to realize the arbitrary frequency response in a real system. An oscilloscope prototype is proposed to verify the calibration performance. The simulation and experiment show the following: (i) Even though it uses the general frequency response and the FRMs are significant, the proposed method is still effective. (ii) The mismatch range of magnitude and phase responses is highly suppressed, and the spurious-free dynamic range is improved by 16.26 dB after calibration of the prototype.

Calibration of Offsets in Time-Interleaved ADCs in an OFDM Receiver Using Differential Evolution Algorithm

Calibration of Offsets in Time-Interleaved ADCs in an OFDM Receiver Using Differential Evolution Algorithm

Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

The time-interleaved analog-to-digital conversion (TIADC) technique is an effective method for increasing the sampling rate in a waveform digitization system. In this study, a 20-Gsps TIADC system was designed. A wide-bandwidth performance was achieved by optimizing the analog circuits, and a sufficient effective number of bits (ENOB) performance guaranteed using the perfect reconstruction algorithm for mismatch error correction. The proposed system was verified by tests, and the results indicated that a − 3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at 6 GHz were successfully achieved.

Testing and Evaluation of a 20-Gsps High-Resolution Waveform Digitizer Based on TIADC Technique

Time-Interleaved Analog-to-Digital Conversion (TIADC) is one of the significant technique in high speed waveform digitization systems. In our latest work, a 20-Gsps 12-bit TIADC system is designed and a series of tests are conducted on the proposed system and a broadband mismatch error correction is implemented. The test methods and results are specifically presented in this paper. The test results show that the -3dB bandwidth of the proposed system is 6 GHz and the ENOB performance is about 8.7 bits at 647 MHz and 7.6 bits at 6 GHz which is significantly enhanced by the mismatch error correction process.

Performance Limits of Generalized Sampling Based 2-Channel Analog-to-Digital Converter

This brief proposes an analog-to-digital converter (ADC) based on Generalized Sampling Theorem and derives a closed form expression of its performance, viz., signal-to-quantization noise ratio (SQNR) and alias-suppression (AS). The ADCs in the 2-channels sample the signal and its filtered version, respectively, at half the Nyquist rate. The outputs of the two ADCs are upsampled by a factor of 2, passed through appropriate reconstruction filters, and then added to give an effective sample-rate which is double that of the sample-rate of each channel ADC. Performance of the proposed ADC has been summarized for simple filters like differentiator, integrator, passive RC low-pass filter, and passive CR high-pass filters. The proposed ADC could therefore be used as an alternative to other popular ADC structures like time-interleaved, frequency-interleaved, and filter-bank ADCs, to achieve high sample-rate with minimal analog circuit overhead.

Correlation-based reconfigurable blind calibration for timing mismatches in TI-ADCs

Mismatches between sub-channels limit the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). This paper proposes a correlation-based method of calibration for timing mismatches in M-channel TI-ADCs by using the cross-correlation between sub-channels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order distortion, which is approximated by multiplying the distortions with the estimated coefficients of mismatch. Furthermore, a reconfigurable strategy composed of stages of arbitrary calibration is proposed to achieve suitable stages with the requisite dynamic performance. Finally, the calibration performance of the proposed method is verified through simulations that use different input signals and strengths of mismatch.

A Background Correlation-Based Timing Skew Estimation Method for Time-Interleaved ADCs

This paper presents a correlation-based all-digital background estimation method for timing skew mismatches in time-interleaved analog-to-digital converters (TI-ADCs). Exploiting the first-order approximation of an autocorrelation function of the digital output of each Sub-ADC, the timing skew mismatch between adjacent channels is identified, which can be used for analog or digital correction methods. The proposed estimation method has a low computation complexity and a simple implementation structure, because it basically only requires multiply-accumulate and average operations. In addition, the proposed method is not limited in the number of channels, does not need any pilot injection, is basically suitable for any bandlimited analog input signal, possess a large estimation range of mismatches and is immune against gain and offset mismatches to a certain extent. Simulation results of a four-channel TI-ADC behavioral model and measurement results from a commercial 12-bit 3.6-GS/s TI-ADC show the effectiveness and superiority of the proposed estimation method.

Closed-Form Expression for the Combined Effect of Offset, Gain, Timing, and Bandwidth Mismatch in Time-Interleaved ADCs Using Generalized Sampling

The performance of a time-interleaved analog-to-digital converter (TI-ADC) gets compromised due to offset , gain mismatch , timing mismatch , and bandwidth mismatch . This article analyzes a TI-ADC from a generalized sampling perspective and then develops closed-form expression of the signal-to-noise and distortion ratio (SNDR) of an $N$ -channel TI-ADC when all of gain mismatch , timing mismatch , and bandwidth mismatch are present at the same time. The analysis is then extended to incorporate the effect of offset along with the other three mismatches to arrive at closed-form expression of SNDR in the presence of all the mismatches. The closed-form expressions have been validated through numerical simulations as well.

TI-ADC multi-channel mismatch estimation and calibration in ultra-high-speed optical signal acquisition system.

This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.