Abstract
The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.
Highlights
The possibility of different sample rate choices in digital storage oscilloscopes (DSOs) is typically implemented by means of a digital circuit, positioned between the analog to digital converter (ADC) and the acquisition memory, that can seamlessly decimate the digitized signal by an integer factor [1,2,3]
The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate
This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate
Summary
The possibility of different sample rate choices in digital storage oscilloscopes (DSOs) is typically implemented by means of a digital circuit, positioned between the analog to digital converter (ADC) and the acquisition memory, that can seamlessly decimate the digitized signal by an integer factor [1,2,3]. Mis the decimation factor [4,5] This ingenious approach lets the ADC steady operate at a fixed-frequency, which is chosen equal to the maximum frequency for which it has been designed, and assures stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate [6,7,8]. A time base system that allows selecting the sample rate with very fine frequency resolution has recently been proposed in [20,21] This solution improves the digital circuit deployed between the ADC and the acquisition memory such that it can digitally downsample the signal by a factor within the interval Throughout the article the attention is mainly paid to illustrate methods and operation principles in the clearest possible way, preferring to this end some degree of abstraction in place of a faithful description of the layout of the digital circuit that implements the proposed solution
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