Combined Power Ratio Calculation, Hadamard Transform and Least Mean Squares Algorithm for Channel Mismatch Calibration in Time-Interleaved ADCs

Abstract

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog-to-digital converters (TIADCs). The average technique is used to remove offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the sub-ADC over the reference ADC. The timing skew mismatch is calibrated by using Hadamard transform for error correction and LMS for timing mismatch estimation. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations. Besides, achievement results on the field-programmable gate array (FPGA) hardware have demonstrated the effectiveness of the proposed techniques.
 KeywordsTime-interleaved analog-to-digital converter (TIADC), channel mismatches, all-digital background calibration
 References[1] Melamed and S. Toledo, A robust, selective, and flexible RF front-end for wideband sampling receivers, ICT Express 3(2) (2017) 96-100.[2] C. Black and D. A. Hodges, Time interleaved converter arrays, IEEE Journal of Solid-state circuits 15(6) (1980) 1022-1029.[3] Razavi, Design considerations for interleaved ADCs, IEEE Journal of Solid-State Circuits 48(8) (2013) 1806-1817.[4] Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, Explicit analysis of channel mismatch effects in time-interleaved ADC systems, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 48(3) (2001) 261-271.[5] Vogel, The impact of combined channel mismatch effects in time-interleaved ADCs, IEEE transactions on instrumentation and measurement 54(1) (2005) 415-427.[6] J. Harpe, J. A. Hegt, and A. H. van Roermund, Analog calibration of channel mismatches in time‐interleaved ADCs, International Journal of Circuit Theory and Applications 37(2) (2009) 301-318.[7] Camarero, K. B. Kalaia, J.-F. Naviner, and P. Loumeau, Mixed-signal clock-skew calibration technique for time-interleaved ADCs, IEEE Transactions on Circuits and Systems I: Regular Papers 55(11) (2008) 3676-3687. DOI: 10.1109/TCSI.2008.926314.[8] Le Duc, D. M. Nguyen, C. Jabbour, T. Graba, P. Desgreys, and O. Jamin, All-digital calibration of timing skews for TIADCs using the polyphase decomposition, IEEE Transactions on Circuits and Systems II: Express Briefs 63(1) (2015) 99-103.[9] Le Duc, D. M. Nguyen, C. Jabbour, T. Graba, P. Desgreys, and O. Jamin, Hardware implementation of all digital calibration for undersampling TIADCs, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 2181-2184.[10] Guo, S. Tian, and Z. Wang, Estimation and correction of gain mismatch and timing error in time-interleaved ADCs based on DFT, Metrology and Measurement Systems 21(3) (2014) 535-544.[11] Qiu, Y.-J. Liu, J. Zhou, G. Zhang, D. Chen, and N. Du, All-digital blind background calibration technique for any channel time-interleaved ADC, IEEE Transactions on Circuits and Systems I: Regular Papers 65(8) (2018) 2503-2514.[12] Matsuno, T. Yamaji, M. Furuta, and T. Itakura, All-digital background calibration technique for time-interleaved ADC using pseudo aliasing signal, IEEE Transactions on Circuits and Systems I: Regular Papers 60(5) (2013) 1113-1121.[13] Saleem and C. Vogel, On blind identification of gain and timing mismatches in time-interleaved analog-to-digital converters, in 33rd International Conference on Telecommunications and Signal Processing, Baden (Austria), 2010, pp. 151-155.[14] W. Kang, H.-K. Hong, S. Park, K.-J. Kim, K.-H. Ahn, and S.-T. Ryu, A sign-equality-based background timing-mismatch calibration algorithm for time-interleaved ADCs, IEEE Transactions on Circuits and Systems II: Express Briefs 63(6) (2016) 518-522.[15] H. Chen, J. Lee, and J.-T. Chen, Digital background calibration for timing mismatch in time-interleaved ADCs, Electronics Letters 42(2) (2006) 74-75.[16] Liu, N. Lv, H. Ma, and A. Zhu, Adaptive semiblind background calibration of timing mismatches in a two-channel time-interleaved analog-to-digital converter, Analog Integrated Circuits and Signal Processing 90(1) (2017) 1-7.[17] Chen, Y. Pan, Y. Yin, and F. Lin, All-digital background calibration technique for timing mismatch of time-interleaved ADCs, Integration 57 (2017) 45-51.[18] Van-Thanh, H. Van-Phuc, and X. Tran, All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs, EAI Endorsed Transactions on Industrial Networks and Intelligent Systems 6(21) (2019). DOI: 10.4108/eai.24-10-2019.160983.[19] Le Dortz et al., 22.5 A 1.62 GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), IEEE, 2014, pp. 386-388.[2] Tertinek and C. Vogel, Reconstruction of nonuniformly sampled bandlimited signals using a differentiator–multiplier cascade, IEEE Transactions on Circuits and Systems I: Regular Papers 55(8) (2008) 2273-2286.[21] Cho et al., Calibration of channel mismatch in time-interleaved real-time digital oscilloscopes, in 2015 85th Microwave Measurement Conference (ARFTG), IEEE, 2015, pp. 1-5.