Abstract
The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.
Highlights
With the remarkable growth of next-generation radio communication systems and the development of the new communication standards, the analog-to-digital converters (ADCs) become the essential components
time-interleaved ADCs (TIADCs) clocked at f s = 2.7 GHz with offset, gain, and timing mismatches as presented in Figure 3 was modeled and simulated in MATLAB software
The offset mismatch was corrected by averaging the output samples of each sub-ADC
Summary
With the remarkable growth of next-generation radio communication systems and the development of the new communication standards, the analog-to-digital converters (ADCs) become the essential components. Taking the advantages of CMOS scaling and portability between technology nodes, all-digital calibration techniques eliminate the above analog and mixed-signal issues [13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31] These techniques often focus on one or two types of mismatches among the gain and timing mismatches, without the offset mismatch [13,14,15,16,17,18,19,20,21,22,23,24,25]. This work develops an improved all-digital background calibration technique for all offset, gain, and timing mismatches with field programmable gate array (FPGA) hardware validation to further enhance the calibration efficiency in TIADCs and provide a solution for designing high speed.
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