All-digital background calibration of gain and timing mismatches in time-interleaved ADCs using adaptive noise canceller

Abstract

This paper proposes a novel all-digital background calibration technique for gain and timing mismatches in Time-Interleaved Analog-to-Digital Converters (TIADCs) using adaptive noise canceller (ANC). The error signals due to the gain and timing mismatches are expressed in linear regression terms, producing the estimation problem of ANC. The gain and clock skew coefficients are estimated by maximizing the output signal-to-noise ratio in ANC system. The correction is simple by subtracting the re-constructed errors from the TIADC output. The proposed calibration technique eliminates the input spectrum constants as well as removes high-pass filters, which are required in the conventional free-band based calibration technique. In order to validate the proposed approach, simulations are carried out for an 11-bit, 2.7GS/s four-channel TIADC for various input signals. Results show that the proposed calibration produces excellent performance in terms of mismatch distortion suppression. It achieves the SNDR and SFDR improvement of 19dB and 49dB, respectively. Moreover, the synthesized design with hardware co-simulation on Xilinx Kintex-7 field-programmable gate array (FPGA) platform consumes only 7.36% of the hardware resources of the FPGA chip and reduces the mismatch tone level up to -87dB.