Time-dependent Dielectric Breakdown Lifetime Research Articles

Physical model for the frequency dependence of time-dependent dielectric breakdown (TDDB)

A molecular physics-based model is presented for understanding the frequency dependence of time-dependent dielectric breakdown (TDDB). The fundamental physics behind the frequency dependence comes from the relative dielectric constant ɛr, which is known to be frequency dependent. A small fractional power-law decrease in dielectric constant with frequency produces a lower local electric field with a significant improvement in TDDB lifetime with frequency.

Impact of Voltage Polarity on Time-Dependent Dielectric Breakdown of 1-nm MgO-Based STT-MRAM With Self-Heating Correction

Time-dependent dielectric breakdown (TDDB) lifetime of ultrathin (1 nm) MgO in spin-transfer torque magnetoresistive random access memory (STT-MRAM) devices has recently been shown to be driven by factors other than voltage alone. This study focuses on the specific role of asymmetry in the current flow for different polarity pulsing modes of voltage stress on the TDDB lifetime of 1-nm MgO. Numerical analysis, based on a 3-D heat-diffusion equation and spintronic simulations, has been performed to characterize the temperature rise in the devices for precise correction of self-heating to obtain a correct interpretation of MgO TDDB. It is shown that the different lifetimes for the positive and negative modes can be attributed to different temperature increases arising from self-heating. While the positive and negative modes displayed a non-Arrhenius behavior, the bipolar mode showed an Arrhenius trend in which we observed a unique bimodal behavior of TDDB activation energy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {a}}$ </tex-math></inline-formula> ) as a function of stress voltage in the ultrathin MgO stack. We discuss the role of additional driving forces, such as current, self-heating, charge trapping, and interface strain governing the breakdown mechanism along with the voltage effect.

Investigation of the Combined Effect of Total Ionizing Dose and Time-Dependent Dielectric Breakdown on PDSOI Devices.

The combined effect of total ionization dose (TID) and time-dependent dielectric breakdown (TDDB) of partially depleted silicon-on-insulator (PDSOI) NMOSFET is investigated. First, the effect of TDDB on the parameter degradation of the devices was investigated by accelerated stress tests. It is found that TDDB stress leads to a decrease in off-state current, a positive drift in threshold voltage, and a reduction of maximum transconductance. Next, the degradation patterns of TID effect on the devices are obtained. The results show that the parameter degradation due to gamma radiation is opposite to the TDDB stress. Finally, the combined effect of TID and TDDB is investigated. It is found that the drift of the devices’ sensitive parameters due to TDDB stress decreases in a total dose of gamma radiation environment. The TDDB lifetime is shortened, but the pattern of gate current change remains unchanged. The failure mechanism of the gate oxide layer under TDDB stress is not changed after irradiation.

Significant Differences in BTI and TDDB Characteristics of Commercial Planar SiC-MOSFETs

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been produced by several vendors for commercial applications. SiC-MOSFET reliability was assessed using bias-temperature instability (BTI) and time-dependent dielectric breakdown (TDDB) characteristics. Here, we compared two planar SiC-MOSFET samples (A and B) from different vendors. The samples exhibited significantly different positive and negative BTI, time-dependent gate-current, TDDB lifetime statistics, and temperature dependence. These differences suggest NO (nitric oxide)-annealing variations.

Large-Area Uniform 1-nm-Level Amorphous Carbon Layers from 3D Conformal Polymer Brushes. A "Next-Generation" Cu Diffusion Barrier?

A reliable method for preparing a conformal amorphous carbon (a-C) layer with a thickness of 1-nm-level, is tested as a possible Cu diffusion barrier layer for next-generation ultrahigh-density semiconductor device miniaturization. A polystyrene brush of uniform thickness is grafted onto 4-inch SiO2 /Si wafer substrates with "self-limiting" chemistry favoring such a uniform layer. UV crosslinking and subsequent carbonization transforms this polymer film into an ultrathin a-C layer without pinholes or hillocks. The uniform coating of nonplanar regions or surfaces is also possible. The Cu diffusion "blocking ability" is evaluated by time-dependent dielectric breakdown (TDDB) tests using a metal-oxide-semiconductor (MOS) capacitor structure. A 0.82nm-thick a-C barrier gives TDDB lifetimes 3.3× longer than that obtained using the conventional 1.0nm-thick TaNx diffusion barrier. In addition, this exceptionally uniform ultrathin polymer and a-C film layers hold promise for selective ion permeable membranes, electrically and thermally insulating films in electronics, slits of angstrom-scale thickness, and, when appropriately functionalized, as a robust ultrathin coating with many other potential applications.

Reliability Analysis on TiN Gated NMOS Transistors

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

Impact of O2 post oxidation annealing on the reliability of SiC/SiO2 MOS capacitors* *Project supported by the General Program of the National Natural Science Foundation of China (Grant No. 61974159) and the Youth Innovation Promotion Association of the Chinese Academy of Sciences and Scientific Instrument Developing Project of the Chinese Academy of Sciences (Grant No. YJKYYQ20200039).

The effects of dry O2 post oxidation annealing (POA) at different temperatures on SiC/SiO2 stacks are comparatively studied in this paper. The results show interface trap density (D it) of SiC/SiO2 stacks, leakage current density (J g), and time-dependent dielectric breakdown (TDDB) characteristics of the oxide, are affected by POA temperature and are closely correlated. Specifically, D it, J g, and inverse median lifetime of TDDB have the same trend against POA temperature, which is instructive for SiC/SiO2 interface quality improvement. Moreover, area dependence of TDDB characteristics for gate oxide on SiC shows different electrode areas lead to same slope of TDDB Weibull curves.

Anomalous Behavior of Gate Current and TDDB Lifetime by Constant Voltage Stress in NO-Annealed SiC-MOSFETs

Silicon-carbide metal–oxide–semiconductor field-effect transistors (SiC-MOSFETs) are core devices for future power electronics. The factors limiting their automotive applications are currently under investigation. Postoxidation annealing in NO gas is a key technology to achieving high carrier mobility in SiC-MOSFETs. In this article, we study the NO annealing effects on time-dependent dielectric breakdown (TDDB) reliability by the constant voltage stress (CVS) method at room temperature (RT). We show that heavy NO annealing enhances hole trapping near the SiO2/SiC interface and leads to a rapid increase in the gate current ( $I_{\text {g}}$ ) and results in shorter time-to-breakdown ( $t_{\text {BD}}$ ) and smaller Weibull slope of $t_{\text {BD}}$ in comparison to light NO annealing case. However, the detailed examination of the $I_{\text {g}}$ behavior reveals that the charge-to-breakdown ( $Q_{\text {BD}}$ ) and its distribution do not deteriorate. Therefore, we must reconsider the use of the CVS method by examining the $I_{\text {g}}$ behavior during stress, which strongly depends on NO annealing conditions.

The influence of Mn doping on the leakage current mechanisms and resistance degradation behavior in lead zirconate titanate films

The electrical reliability of lead zirconate titanate (PZT) films was improved by incorporating Mn; the time dependent dielectric breakdown lifetimes and the associated activation energy both remarkably increased with Mn concentration. The correlation between the defect chemistry and the resistance degradation was studied to understand the physical mechanism(s) responsible for enhanced electrical reliability. At lower electric fields, Poole-Frenkel emission was responsible for the leakage current. Beyond a threshold electric field, Schottky emission controlled the leakage. After electrical degradation of a 2 mol.% Mn doped PZT film, no significant change in potential barrier height for injecting electrons from the cathode into the anode was observed. This suggests that the degradation is mostly controlled by Poole-Frenkel conduction via some combination of hole migration between lead vacancies, small polaron hopping between Mn sites, and hole hopping between Pb2+ and Pb3+. No variation in the valence state of Ti near the cathode was observed in degraded Mn doped PZT films, implying that multivalent Mn provides trap sites for electrons and holes; free electron generation due to compensation of oxygen vacancies at the cathode and free hole formation at the anode region might be suppressed by the valence changes from Mn3+ to Mn2+ and Mn2+ to Mn3+ respectively.

Reliability Characteristics of Diamond-Like Carbon as Gate Insulator for Metal–Insulator–Semiconductor Application

This study presents the reliability of diamond-like carbon (DLC) ultrathin films fabricated by DC magnetron sputtering as the gate dielectric layer in metal–insulator–semiconductor (MIS) devices. Stress-induced leakage current (SILC) and time-dependent dielectric breakdown (TDDB) measurements were performed to determine the reliability of the devices. The MIS device with DLC film deposited at 1100-V bias exhibited little variation of SILC under different constant voltage stress times and had a long TDDB lifetime. The results indicate excellent reliability of DLC films used as gate dielectrics. Moreover, several soft breakdown events occurred during TDDB measuring. An extended percolation model was adopted for explanation of the current versus time characteristics.

TDDB Lifetime Enhancement in SiC-MOSFETs under Gate-Switching Pperation

Gate oxide integrity (GOI) are the most important concern in automotive applications of SiC-metal-oxide-semiconductor field-effect transistors (MOSFETs). As well as for the so-called B-mode defect density reduction, the time-dependent dielectric breakdown (TDDB) mechanism including the B-mode should be clarified in comparison to Si-MOSFETs. We have reported an anomalous behavior in the form of a continuous increase in the gate current during a Fowler-Nordheim stress test of commercially available SiC-MOSFETs, which we attributed to hole trapping near the SiO2/SiC interface. In this paper, the impact of this phenomenon on the TDDB lifetime is investigated, and the effects of AC on the TDDB lifetime enhancement in SiC-MOSFET under gate-switching operations (1 kHz and 100 kHz, at room temperature) are reported.

Improved electrical characteristics and reliability of p-MOSFET with fluorine implant

The method of fluorine implant directly after a poly gate deposition process step is proposed to improve both electrical characteristics and reliabilities by creating Si-F bonding at a gate oxide interface and negative fixed charged in a gate oxide. Capacitance-voltage (C-V) curve and gate oxide leakage current was used to investigate oxide thickness and flat band voltage (Vfb) shift. Experimental results show fluorine implant induced regrowth of gate oxide ~1 Å and Vfb shift ~−40 mV. Owing to the Vfb shift, ~24 mV of drain induced barrier lowering is improved. Furthermore, gate oxide interface quality was evaluated using charge pumping current and negative bias temperature instability (NBTI), and gate oxide quality was evaluated using time-dependent dielectric breakdown (TDDB). The results show that the fluorine implant process which is prosed in this paper reduced 27% of the interface trap and improved ~0.8 order higher NBTI lifetime. TDDB lifetime showed a slight improvement when using the proposed method. Thus, a controlled fluorine implant step improves both DC electrical characteristics and gate oxide reliabilities. These suggest that the fluorine implant step should be carefully selected when fabricating PMOSFETs.

High reliability CoFeB/MgO/CoFeB magnetic tunnel junction fabrication using low-damage ion beam etching

In this work, the impact of pattern edge of MgO films due to electrode separation process on its electrical reliability was investigated by measuring and analyzing I–V and time-dependent dielectric breakdown (TDDB) characteristics of MgO films with different pattern edge length. The measured TDDB lifetime at 63% drastically decreased from 1440 to 2 s when the pattern edge length increased from 32 to 320 μm, thus the electric reliability of MgO films can be significantly degraded due to the pattern edge. It was found that this issue can be solved by improving the process condition of ion bean etching (IBE), by turning the IBE angle and the IBE angle divergence. These findings can lead to high reliability magnetic tunnel junction fabrication in spin-transfer torque magnetic random access memory.

Effect of Post-Annealing on Reliability of Cu/Low-k Interconnects

Due to the continuous increase of multilevel Cu/low-k interconnects, the total thermal budget has been increasing. As a result, the effects of post-annealing on the time-dependent-dielectric-breakdown (TDDB) and electromigration (EM) reliability of Cu/low-k interconnects were investigated in this study. Dense and porous low-k SiCOH dielectric films without or with an SiCNH capping layer were used for comparison. Post-annealing reduced TDDB lifetimes for dense and porous SiCOH dielectric films without a capping layer. With an SiCNH capping layer, annealing at 400 °C had no impact on TDDB lifetime due to the suppression of Cu migration induced breakdown. However, as the annealing temperature increased to 600 °C, both dense and porous SiCOH dielectric films displayed a significant reduction in TDDB lifetimes. The SiCNH capping layer is crucial for EM lifetime improvement due to the reduction of Cu surface migration. With an SiCNH capping layer, the post-annealing influencing EM lifetimes depended on the flow direction of electron. In the case of electron up-flow, EM lifetimes remained unchanged for both dense and porous low-k dielectrics upon annealing at 400 °C. While for electron down-flow case, annealing at 400 °C degraded EM lifetime and the reduction was pronounced for porous dielectric films.

Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal Layers

Air-gap (AG) technology on back-end-of-line (BEOL) provides a means to improve performance without area or power degradation. However, the “blind” use of AG based on traditional design methodologies does not provide sufficient performance gain. We developed an AG-aware design methodology to maximize performance gain with minimum cost. The experimental results of the proposed methodology, which was tested using a 10 nm Advanced RISC Machine (ARM) Cortex-A9 quad-core central processing unit (CPU), indicated a performance gain of 6.1–8.4% compared with traditional AG design. The performance gain achieved represents about half of the 10–15% performance improvement under the same power by a process node shrink. A Si process of consecutive double AG layers was developed by overcoming various process challenges, such as AG depth control, Cu/ultra-low-k damage, the hermetic AG liner, and step-height control above the AG. Furthermore, the capacitance was reduced by 17.0%, which satisfied the target goal in the simulation stage for the assumed structure. The optimized integration process was validated according to the function yield of the CPU, which was comparable to that of a non-AG process. The time-dependent dielectric breakdown and electromigration lifetime of the AG wire satisfied the 10-year criteria, and the assembly yield was verified.

Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis

Time-dependent dielectric breakdown (TDDB) has become an important cause of failure for inter-metal dielectrics (IMD) in integrated circuits as feature sizes continue to shrink and novel materials are introduced. Although many studies have been conducted to understand the underlying physics of this issue, not enough work has been focused on evaluating TDDB lifetime of practical chip designs in the physical design stage. This paper proposes a full-chip TDDB failure analysis methodology to evaluate lifetime and identify TDDB hotspots in VLSI layouts, which are essentially interconnect wires that have high failure risk due to TDDB. The proposed method features three new techniques compared to existing methods. First, we have developed a partitioning-based scheme to deal with scaling of full-chip analysis by partitioning the full chip layout into small tiles. Second, for each tile, the new method calculates a newly-introduced TDDB failure metric called TDDB Damage for vulnerable wires. Such a wire-oriented TDDB analysis is the first of its kind and is very amenable for physical design as the wires can be easily adjusted or re-routed for TDDB-aware optimization. Third, the new method considers the impact of the non-uniform electric field calculated using the finite element method (FEM), which significantly improves the accuracy of TDDB risk evaluation. Experimental results show that the proposed new TDDB analysis method is more accurate than a recently proposed full-chip TDDB analysis method in which electrical field is treated as a constant value. Additionally, the proposed method can analyze a practical VLSI layout in a few hours.

Investigating the latent reliability degradation of partially depleted SOI devices induced by high-energy heavy ions irradiation

Through electrical stress and annealing experiments performed on irradiated partially depleted SOI MOS devices, high-energy heavy ions induced defects in the gate oxide are shown to affect insulation character and the long time reliability of the devices. A decrease of the time-dependent dielectric breakdown (TDDB) lifetime and an increase of the radiation-induced leakage current (RILC) were observed after irradiation at the nominal operating irradiation bias. But then, the RILC was completely removable using isochronal annealing experiment, while the TDDB lifetime did not increase back to its initial value. We interpreted these results and degeneration mechanisms in terms of the neutral electrons traps and morphological oxide defects induced by high-energy heavy ions, which may be meaningful to evaluate the reliability of the devices used in the radiation environment.

Improved Interface Properties and Dielectric Breakdown in Recessed AlGaN/GaN MOS-HEMTs Using HfSiO&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$_{{x}}$ &lt;/tex-math&gt; &lt;/inline-formula&gt; as Gate Dielectric

In this letter, we report optimized transport properties in gate recessed enhancement-mode GaN MOS-HEMTs by incorporating silicon into atomic layer deposited gate dielectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Compared with commonly used HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric, the interface trap density can be reduced by nearly an order of magnitude and the fixed oxide traps inside are reduced to almost half using the high-quality passivation of HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> . The MOS-HEMTs based on HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> exhibit a threshold voltage of 1.5 V, excellent subthreshold swing of 65 mV/dec, and a high on-off ratio of 3 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> . The incorporation of silicon in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> can also increase the dielectric breakdown property with maximum gate electric field of 2.85 MV/cm for a 10-year time-dependent gate dielectric breakdown lifetime, which is 36% higher than pure HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The maximum breakdown voltage of HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> MOS-HEMT is 742 V, which is 30% higher than HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> MOS-HEMT.

Effects of Copper Migration on the Reliability of Through-Silicon Via (TSV)

Non-destructive electrical characterization was performed to detect copper migration in a degraded through-silicon via structure after various stressing conditions, such as elevated temperature exposure, temperature cycling, and electrical biasing. They were performed either independently or as a combination with electrical bias for comparison. Variations in the electrical characteristics reflect the presence of copper. The electrical characteristics were also able to monitor the transport of copper ions from an applied electric field. Physical failure analysis was performed to verify the presence of migrated copper, correlating with the changes observed during electrical measurement. With this understanding, reliability assessments become possible where this paper seeks to value add to verify the influence of Cu migration on the conduction mechanism and time-dependent dielectric breakdown (TDDB) lifetime, in which there is currently a lack in understanding. The conduction mechanism was fitted with experimental data before and after degradation and it was deduced that the Poole–Frenkel conduction mechanism is the dominant mechanism after degradation. However, this is dependent on the copper oxidation state which was verified to change over time from Cu2O to CuO by X-ray photoelectron spectroscopy. TDDB experiments were also performed based on this understanding and found that the presence of copper may accelerate or decelerate time to failure. TDDB lifetime was fitted experimentally and is found to be in good agreement with the $\sqrt {E} $ model. It was verified experimentally by measuring the time to failure at low ${E}$ -field within reasonable failure time, rather than extrapolating from data at high field.

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit’s lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology.