Timing Criticality-Aware Design Optimization using BEOL Air Gap Technology on Consecutive Metal Layers

Ryu Ryu,Cho Cho,Han Han

doi:10.3390/electronics8111274

Abstract

Air-gap (AG) technology on back-end-of-line (BEOL) provides a means to improve performance without area or power degradation. However, the “blind” use of AG based on traditional design methodologies does not provide sufficient performance gain. We developed an AG-aware design methodology to maximize performance gain with minimum cost. The experimental results of the proposed methodology, which was tested using a 10 nm Advanced RISC Machine (ARM) Cortex-A9 quad-core central processing unit (CPU), indicated a performance gain of 6.1–8.4% compared with traditional AG design. The performance gain achieved represents about half of the 10–15% performance improvement under the same power by a process node shrink. A Si process of consecutive double AG layers was developed by overcoming various process challenges, such as AG depth control, Cu/ultra-low-k damage, the hermetic AG liner, and step-height control above the AG. Furthermore, the capacitance was reduced by 17.0%, which satisfied the target goal in the simulation stage for the assumed structure. The optimized integration process was validated according to the function yield of the CPU, which was comparable to that of a non-AG process. The time-dependent dielectric breakdown and electromigration lifetime of the AG wire satisfied the 10-year criteria, and the assembly yield was verified.

Highlights

The scaling of large-scale integration technology has significantly increased the parasitic resistance and capacitance in multilevel interconnects
There are two types of air gap (AG) processes: (1) removal of the sacrificial material via thermal decomposition or chemical treatment [6,7,8,9,10] through the upper dielectric layer and (2) etching back the intermetal dielectrics (IMDs) followed by pinch-off of the IMD deposition [11,12,13,14,15]
The performance by only 0.6% with two AG layers, whereas a 2.2% performance gain was observed when the AG was improved by only 0.6% with two AG layers, whereas a 2.2% performance gain was observed when applied to all six routing metal layers

Summary

Introduction

The scaling of large-scale integration technology has significantly increased the parasitic resistance and capacitance in multilevel interconnects. Low-k materials are widely used as intermetal dielectrics (IMDs) and interlayer dielectrics to enhance circuit performance and reduce power consumption [1,2]. The use of low-k materials is challenging owing to their mechanical strength and process immunity properties, which are degraded with the reduction of the k-value [3]. This is generally caused by breakage of the strong Si-O network through Si-CH3 termination, yielding low permittivity, and by the introduction of tiny pores in the matrix, which allow air to enter the dielectric material [4,5]. There are two types of AG processes: (1) removal of the sacrificial material via thermal decomposition or chemical treatment [6,7,8,9,10] through the upper dielectric layer and (2) etching back the IMD followed by pinch-off of the IMD deposition [11,12,13,14,15]

Methods

Results

Conclusion