Time-dependent Dielectric Breakdown Lifetime Research Articles

Influence of CMP Slurries and Post-CMP Cleaning Solutions on Cu Interconnects and TDDB Reliability

We investigated Cu/low-k integration to test the time-dependent dielectric breakdown (TDDB) reliability of Cu interconnects. We described the relationship between TDDB lifetime and defects possibly caused by the Cu chemical-mechanical polishing (CMP) process, such as rough copper surface corrosion, crevice corrosion, and scratches, using Cu/silicon oxycarbide interconnects. Although rough copper surface corrosion has an insignificant effect on the TDDB lifetime, crevice corrosion at the edges of wires does cause TDDB degradation. We also found that a structure’s TDDB lifetime was affected by the kind of post-CMP cleaning solutions used when barrier metal slurries do not contain benzotriazole (BTA). These results indicate that two types of processes for post-CMP cleaning should be used. It is best to use solutions that do not have strong oxidized copper dissolution ability but can remove particles when a barrier metal slurry with an inhibitor other than BTA is used. Also good are solutions with a strong oxidized copper dissolution ability that have been optimized to prevent Cu corrosion when a barrier metal slurry with BTA is used. To improve TDDB reliability, care must be taken with regard to the combination of the barrier metal slurry and the post-CMP cleaning solution.

Cathode Electron Injection Breakdown Model and Time Dependent Dielectric Breakdown Lifetime Prediction in High-k/Metal Gate Stack p-Type Metal–Oxide–Silicon Field Effect Transistors

We have investigated the time dependent dielectric breakdown (TDDB) for a high-k/metal gate p-type metal–oxide–semiconductor field effect transistors (pMOSFETs) under inversion stress. We have found that electrons, injected from the cathode, are minority carriers in the gate leakage current and play an important role in determining TDDB lifetime and that the existence of oxygen vacancies in HfSiON, decide the electron current mechanism in HfSiON. Since electrons from the cathode flow as a tunneling current with the effective barrier height determined by the energy level of the oxygen vacancies in the HfSiON, electron current is strongly dependent on the effective work function of the metal gate. That implies that a higher work function should be effective to suppress of electron current, due to the elevated barrier height for electrons. Therefore, the formation of a high work function metal gate is essential, not only for low threshold voltage of pMOSFETs but also to achieve long TDDB lifetimes.

Characterization of Line-Edge Roughness in Cu/Low-k Interconnect Pattern

To establish a method of measuring interconnect line-edge roughness (LER), low-k line patterns were observed and electric field concentration was simulated on the basis of observation results. Wedge-shaped LERs were observed at the edges of low-k lines, and the bottom and the top widths of the average wedge feature were 60 and 7 nm (or smaller), respectively. Simulation showed that LER causes serious electric field concentration, which may cause the degradation of time-dependent dielectric breakdown (TDDB) lifetime at 100-nm-pitch Cu/low-k interconnects. The maximum electric field strength depends on the conventional LER metric 3Rq, but depends more strongly on the wedge angle, the curvature of the tip. That is, other metrics such as wedge angle can predict fatal electric field concentration caused by LER than the conventional metric 3Rq.

Performance and Reliability Improvement by Optimizing the Nitrogen Content of the TaSiNx Metal Gate in Metal/HfSiON n-Type Field-Effect Transistors

We have investigated the impacts of the nitrogen content in a TaSiNx metal gate on the performance of metal/HfSiON n-type field-effect transistors (FETs). To obtain a low threshold voltage and low electrode resistance, low nitrogen concentration in TaSiNx is preferable. However, the use of a TaSi gate ([N] = 0%) causes the degradation of HfSiON dielectric characteristics such as an increase in leakage current under gate negative bias, positive-bias temperature instability lifetime degradation, time-dependent dielectric breakdown lifetime degradation, and reduction of the electron mobility. Then, a low-nitrogen-concentration TaSiN ([N] = 20%) gate shows the highest electron mobility, excellent reliability characteristics, and low threshold voltage.

Fundamental reliability of 1.5‐nm-thick silicon oxide gate films grown at 150°C by modified reactive ion beam deposition

The reliability of 1.5‐nm-thick silicon oxide gate films grown at 150°C by modified reactive ion beam deposition (RIBD) with in situ pyrolytic-gas passivation (PGP) using N2O and NF3 was investigated. RIBD uses low-energy-controlled reactive, ionized species and potentializes low-temperature film growth. Although the oxide films were grown at a low temperature of 150°C, their fundamental indices of reliability, such as the time-dependent dielectric breakdown lifetime and interface state density, were almost equivalent to those of oxide films grown at 850°C using a furnace. This is probably due to localized interfacial N and F atoms. The number density of interfacial N atoms was about seven times larger than that for the furnace-grown oxide films, and this is a key factor for improving the reliability through the compensation of residual inconsistent-state bonding sites.

Low Stand-by Power HfSiON Transistor Design Scheme Ensuring Both Performance and Time Dependent Dielectric Breakdown Lifetime for 65 nm Node and Beyond

We have proposed a 65 nm node low stand-by power (LSTP) HfSiON/base-SiO2 transistor design scheme ensuring both high performance and reliability at the same time. In particular, a process condition around the gate was carefully designed. It was found that a low temperature SiO2 offset-spacer could remove the nonintrinsic factor for time-dependent dielectric breakdown (TDDB) without performance degradation. Moreover, a method of monitoring gate leakage after gate dielectric breakdown has been introduced to improve TDDB lifetime. This method can sense extrinsic factors that induce TDDB lifetime degradation. Using this method, we successfully eliminated extrinsic factors that are related to process conditions. Consequently, TDDB lifetime can be guaranteed at Vdd = 1.2 V without performance degradation.

Accurate TDDB Lifetime Prediction of High-k Stacked Gate Dielectrics with Regarding High Density Initial Traps

Essentials required for the accurate TDDB lifetime (TBD) prediction of high-k stacked gate dielectrics are discussed. For this purpose, thorough understanding of the time dependent dielectric breakdown (TDDB) mechanism is indispensable, along with clarifying its stress gate voltage (VG) dependence. As for the TDDB mechanism, we propose the Generated Subordinate Carrier Injection (GSCI) model, which presumes that the degradation is dominated by the injected subordinate carriers (IDC). Because of the coexistence of the current component which does not contribute to the breakdown such as the trap-assisted current, the decomposition of the subordinate carrier current to each component is needed. On the other hand, to obtain the stress VGdependence of TBD, we point out the universal relationship between the voltage acceleration factor of TBD and the stress VG. It is demonstrated that the accurate lifetime prediction can be realized on the basis of the GSCI model combined with this universality.

Time-Dependent Dielectric Breakdown Characterization of 90- and 65-nm-Node Cu/SiOC Interconnects with Via Plugs

As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm were carried out by a package TDDB method with high temperature up to 300 °C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300 °C at 1.8 MV/cm. The activation energies for the 90 and 65 nm nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.

Plasma-Enhanced-Polymerization Thin-Film as a Drift Barrier for Cu Ions

The barrier properties of divinyl siloxane-benzocyclobutene (DVS-BCB) films formed by plasma-enhanced polymerization were studied for ultralow-k porous silica (po-SiO) interlayer dielectrics. Time-dependent dielectric breakdown (TDDB) measurements of blanket Cu/BCB/Si metal–insulator–semiconductor (MIS) capacitors showed no polarity dependence of the bias-temperature stresses at 200 °C under 2 MV/cm, indicating that Cu ions hardly drifted into the BCB film with the positive bias stress. On the other hand, Cu/SiOC/Si MIS capacitors under the positively biased Cu showed a significant degradation in the TDDB lifetime compared with the negative bias case. The barrier effect of the thin BCB was confirmed from the TDDB measurements using Cu/BCB/ultralow-k-po-SiO/Si stacked MIS structures. The TDDB lifetime of the stacked MIS capacitor was improved more than 30-fold by the use of 15-nm-thick BCB on po-SiO. The electric field and temperature dependences of the TDDB lifetime of the stacked MIS structure indicated that the TDDB lifetime of po-SiO capped with 15-nm-thick BCB is longer than 10 years at 125 °C and 1.4 MV/cm. We conclude that the barrier property of BCB that is as thin as 15 nm is effective for preventing Cu ion drift into interlayer dielectrics.

Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors

Highly reliable metal–insulator–metal (MIM) capacitor with ultra-thin SiN dielectrics is developed on the surface-controlled bottom electrode in nanometer-scales. Coverage of the TiN bottom electrode with a Ta thin layer achieves smooth surface. In addition, this electrode structure exhibits excellent etching controllability even for the MIM with the ultra-thin SiN dielectrics. The smooth surface of the Ta/TiN stacked electrode improves the dielectric characteristics such as leakage, breakdown and time-dependent dielectric breakdown (TDDB) reliability in the MIM capacitors, integrated into Cu dual-damascene interconnects (DDIs). As a result, the SiN-MIM with the Ta/TiN bottom electrode achieves high capacitance of 7 fF/µm2 as well as high reliabilities, which are 20% higher breakdown field and 6000 times longer TDDB lifetime than that without Ta-insertion. These values guarantee the high performance operation for more than 10 years under the environment at 85 °C.

Plasma ash modulation of TDDB thermal activation energy in damascene SiOC:H

During Cu/low-k damascene integration, plasma ash can introduce a thin modified layer on the trench sidewall of low-k dielectrics. This plasma ash modified layer can influence the time-dependent dielectric breakdown (TDDB) lifetime distribution. In this paper, we investigated the plasma ash modified layer effect on the TDDB thermal activation energy of a CVD SiOC:H low-k dielectric (k = 3) integrated in Cu damascene structures. We found that for the ‘non-modified’ SiOC:H low-k dielectric combined with sealing metal diffusion barriers, the TDDB thermal activation energy is close to zero. With the introduction of a plasma ash modified layer, the apparent TDDB thermal activation energy increases. By means of thermal desorption spectroscopy on blanket films and energy-filtered TEM analysis on patterned structures, the increase of TDDB thermal activation energy is correlated with plasma ash induced moisture uptake in the CVD SiOC:H low-k dielectric.

Additional fluorine passivation to pyrolytic-N2O passivated ultrathin silicon oxide/Si(100) films

To enhance the reliability of ultrathin silicon oxide/Si(100) films and clarify the effect of fluorine on it, in situ pyrolytic-gas passivation (PGP) using NF3 was simultaneously performed with the previously proposed PGP using N2O. As a result, the following synergistic effects of F and N passivation for the films were confirmed: The electrical characteristics, such as the time-dependent dielectric breakdown lifetime, potential barrier height energy of the oxide, and interface state density, were significantly improved. Quantitative analyses of F and N indicated that this is probably caused by microscopic structural changes in the oxide near the oxide-Si(100) substrate interface. It is, therefore, believed that F passivation effectively contributes to compensate the inconsistent-state bonding sites near the interface that remain with N passivation.

Electrical Stability and Reliability of Ultralow Dielectric Constant Porous Carbon-Doped Oxide film for Copper Interconnect

Nanoporous carbon-doped oxide (CDO) is a promising low dielectric constant (low-) intermetal dielectric (IMD) for Cu interconnect. The electrical stability and reliability of CDO strongly depend on the contacted metal. An electrical instability model considering metal ion diffusion, dielectric polarization, and carrier injection is proposed for CDO under electrical stress. Both Al and Cu are not suitable for contact with CDO because they can be driven easily into CDO. Fortunately, TaN shows no mobile ion issues when in contact with CDO. The electron transport mechanism is identified to be Schottky emission at low electric field and low temperature. As metal ions are injected into CDO film, the electron transport mechanism changes to Frenkel-Pool emission at high temperature and high electric field. The injection of metal ions into CDO also degrades the time-dependent dielectric breakdown (TDDB) lifetime of CDO. Fortunately, the commonly used diffusion barrier TaN is an excellent contact metal with CDO. The 1-year-long TDDB lifetime allows an electric field stronger than , and the TDDB lifetime at becomes longer than 10 years by several orders of magnitude. It is concluded that the nanoporous CDO is a very promising IMD for next-generation interconnect systems.

Impact of introducing CuSiN self-aligned barriers in advanced copper interconnects

Self-aligned barriers have been widely investigated in the replacement of standard PECVD dielectric liners to decrease coupling capacitance. As an alternative to CVD or electroless approaches, a two step process based on the modification of the Cu surface is proposed. This technique consists first in enriching Cu surface with Si atoms followed by a nitridation step to complete the so called CuSiN self-aligned barrier. In this paper, the silicidation mechanism is described and the crucial role of the nitridation step is demonstrated in terms of barrier stability under electrical stress. CuSiN efficiency against Cu diffusion and oxidation is also evidenced. Compared to a standard SiCN barrier, CuSiN self-aligned barriers revealed a gain of at least 3 decades in time-dependent dielectric breakdown lifetime and up to 7% decrease in intra-level coupling capacitance.

Dominant Factors in TDDB Degradation of Cu Interconnects

The field acceleration factor (/spl gamma/) for the E-model of time-dependent dielectric breakdown (TDDB) in various Cu interconnect structures has been studied. The /spl gamma/ for pSiCN structures is larger than that of pSiN structures and independent of the kind of interlayer dielectric material or other processes used to make it. The relationship between the breakdown electric field strength (E/sub BD/) and the TDDB lifetime has been investigated. It has been demonstrated that the TDDB lifetime can be predicted from experimentally measured E/sub BD/ and /spl gamma/. An E/sub BD/ of at least 4.2 MV/cm is necessary to assure ten-year reliability under 0.2 MV/cm operation. Moreover, the important factors influencing the TDDB lifetime for Cu interconnects have been discussed. These include the Cu chemical-mechanical polishing (CMP), the post-CMP annealing, line edge roughness, and fine line effect.

Dependence of Time-Dependent Dielectric Breakdown Lifetime on NH3-Plasma Treatment in Cu Interconnects

The time-dependent dielectric breakdown (TDDB) between adjacent Cu wires was investigated. TDDB lifetime strongly depends on the conditions of the chemical mechanical polishing (CMP) surface and of NH3-plasma treatment prior to cap nitride deposition. The condition of NH3-plasma treatment was evaluated in detail. The TDDB lifetime is strongly dependent on the substrate temperature and the duration of NH3-plasma treatment but is independent of the pressure and power. Excessive NH3-plasma treatment degrades the TDDB lifetime. Hillocks on the Cu surface appear abruptly as the substrate temperature rises. The optimum treatment conditions are 10–30 s for a substrate temperature of 360°C, and 10 s for a substrate temperature of 400°C.

Influence of Humidity on Electrical Characteristics of Self-Assembled Porous Silica Low-k Films

The influence of humidity on the dielectric constant and leakage current of self-assembled porous silica films which have two-dimensional hexagonal periodic porous structures was investigated quantitatively by proposing a new water adsorption model. The amount of adsorption was calculated by the modified Rayleigh model, where molecules are assumed to be adsorbed on the inner surface of cylindrical porous silica structures and form a dispersal concentric double-layer dielectric cylinder system. The amount of calculated by the proposed model was consistent with the measured dielectric constant and thermogravimetry data. It suggests that inner-surface coverage of the cylindrical porous silica wall with a hydrophobic group is the most effective way to suppress water adsorption. Hexamethyldisilazane as a surface coverage molecule was introduced to the periodic cylindrical porous silica film and the leakage current was suppressed by a factor of even below 0.5% relative humidity, resulting in the improvement of time-dependent dielectric breakdown lifetime by a factor of 30.

Influence of Post-CMP Cleaning on Cu Interconnects and TDDB Reliability

The etching amount of Cu wires produced by post-chemical-mechanical polishing cleaning was studied. By using polyvinyl alcohol brush cleaning, the cleaning strength concentrates on the center chip of the wafer, which leads to the erosion of Cu interconnects. The etching depths of isolated Cu wires and dense Cu wires were compared. The surface on the isolated Cu wires is etched deeply because of the nonliner diffusion of the solution and the difference between the friction strengths of both wire patterns. These etching depths were improved by optimizing the brush formation, the rotation speed of the roller and the brush, and by using organic-acids. With respect to the dependence of time-dependent dielectric breakdown (TDDB) lifetime on waiting time, there is a difference between the diluted hydrofluoric-acid (DHF) and organic-acid solutions. The TDDB lifetime for the DHF cleaning is similar until after a waiting time of ten days, whereas the TDDB lifetimes for organic-acids are similar until after a waiting time of four days.

Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO2 CMOSFETs

The mechanisms of gate leakage current and that of time dependent dielectric breakdown (TDDB) failure of HfSiON/SiO2 gate dielectrics having an equivalent oxide thickness of 1.6 nm were investigated. The leakage current mechanism was found to be different for low and high electric fields, which we attribute to the difference in barrier height between interfacial SiO2 and HfSiON. The mechanism of TDDB also proved to be different for low and high electric fields. Accordingly, TDDB lifetime must be evaluated in the low-gate-bias region, where the leakage current mechanism is the same as that of the actual FET operating voltages. A system for detecting defect generation using an emission microscope was developed, enabling low-bias TDDB measurements of large-gate-area transistors. Through this investigation, it was predicted that HfSiON/SiO2 has much more than 10 years' TDDB reliability.

Influence of Cu-Ion Migration and Fine-Line Effect on Time-Dependent Dielectric Breakdown Lifetime of Cu Interconnects

The time-dependent dielectric breakdown (TDDB) of sub-half-micron Cu interconnects was investigated with respect to the waiting time between Cu chemical mechanical polishing (CMP) and barrier dielectric deposition. Breakdown voltage and TDDB lifetime between adjacent Cu wires decrease markedly if the waiting time in air exceeds 5 days. This is due to Cu-ion migration phenomenon on the CMP surface. The degradation can be improved by keeping the samples in a N2 box or adopting post-CMP cleaning. This TDDB degradation has been observed for various Cu barrier dielectrics in this study. In addition, a “fine-line effect” on Cu TDDB lifetime has been discovered. As Cu wire width becomes smaller, the TDDB lifetime also decreases because of the intensification of the electric field at the CMP surface.