Through Technology Computer-aided Design Research Articles

A fast-switching low-loss field-stop IGBT with dual control gate of SIPOS material

A fast-switching low-loss field-stop insulated gate bipolar transistor with a dual control gate (DIGBT) of a semi-insulating polycrytalline silicon (SIPOS) material is proposed in this paper. Because the SIPOS has uniform high resistance, it has an approximate linear electric potential distribution. When DIGBT conducts, the higher electric potential on SIPOS causes the P-type drift region (P-drift) to generate an inversion layer of electrons, adjusting the number of carriers and making the generation of non-equilibrium carriers no longer dependent on the doping concentration in P-drift (Nd) but on the electric potential distribution on SIPOS. Therefore, it can solve the contradiction among the breakdown voltage, forward voltage drop [VCE(sat)], turn-off time (toff), and turn-off loss (Eoff) caused by the Nd. Through Technology Computer Aided Design (TCAD) simulation, the VCE(sat) of DIGBT is 30.6% lower than that of SJFS IGBT. Meanwhile, DIGBT reduces the toff by 62.8% while reducing the Eoff by 83.0% compared to SJFS IGBT. In addition, the static latch-up I–V and the forward biased safe operating area of the DIGBT have been significantly improved. This paper adjusts the number of carriers through the characteristics of SIPOS material, enabling the above-mentioned physical phenomena to be applied in insulated gate bipolar transistor power devices and achieving device performance breakthroughs.

An investigation into the thermal surface contact resistance, fin width and temperature on negative bias temperature instability during self-heating

This work investigates the impacts of the thermal surface contact resistance (SR), fin width and temperature on the negative bias temperature instability (NBTI) during self-heating based on 14 nm p-FinFET through technology computer-aided design (TCAD) tool. In order to promote the accuracy of simulation, the experimental data are used to calibrate the TCAD results. The simulation results reveal that as SR increases, the lattice temperature rises by 20.07 %, which leads to a 15.84 % decrease of the carrier mobility and finally a reduction of the saturation current by 5.07 %. Moreover, as WFin decreases from 8 nm to 2 nm, the device threshold voltage increases by 15.41 %, resulting in that the saturation current reduces by 19.06 %. Besides, with an increase of the ambient temperature from 300 K to 500 K, the lattice temperature and trapped charge rise by 60.48 % and 12.53 %, respectively, which eventually leads to an 18.13 % decrease of the saturation current.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference.

Efficacy of back barrier engineered Π-gate InAlN/GaN high electron mobility transistors for high-power applications

This work investigates thin-barrier InAlN/GaN high electron mobility transistors (HEMTs) for high-power applications through technology computer-aided design (TCAD) simulations. To begin with, the TCAD simulations were first calibrated with an in-house fabricated InAlN HEMT sample for both DC and pulsed characteristics. The thin-barrier InAlN/GaN HEMTs showed a large leakage current through the gate electrode due to high gate injection, which severely degrades the breakdown characteristics of the device and thus acts as a bottleneck for high-power applications. To improve the two-dimensional electron gas confinement, and consequently reduce the bulk leakage, a back-barrier technique was used. The resistive GaN buffer was replaced with an AlGaN back-barrier that improved the breakdown characteristics at the cost of output power density. Thus, to scale up the output power density and further optimize the breakdown characteristics a Π-shaped gate was introduced to limit the gate leakage current through the InAlN barrier by virtue of its improved hot electron reliability. Coupled with the AlGaN back-barrier, the Π-gate significantly improved the breakdown characteristics to achieve high output power densities, albeit with minor trade-offs to the device gain. To elucidate the compatibility with high-power applications, all the device architectures were dynamically characterized by pulsed I–V simulations and the trap-related dispersive effects were investigated. The Π-shaped gate coupled with an AlGaN back-barrier outperforms conventional architectures by exercising superior electrostatic control over the channel and exhibiting a high linearity for high-power millimeter-wave applications.

A Dual Core Source/Drain GAA FinFET

The emergence of fin-shaped field effect transistors (FinFETs) was governed by the requirement of the VLSI industry to include more functionalities per unit chip area. Enhanced gate control in a FinFET due to a surrounding gate architecture built on the fundamental geometry of a MOSFET made them highly compatible to the existing CMOS circuit applications. The announcement of a vertically stacked multiple FinFET structure named as Ribbon-FET by Intel Corporation in 2021 motivates the work presented in this article. This article proposes a dual core sourcedrain gate-all-around FinFET, and evaluates its performance in terms of variation in core doping concentrations through technology computer aided design (TCAD) simulations. The advantage of having a dual core in source and drain regions is the opportunity to tune the performance metrics of the device by altering the doping concentration in the outer, and inner cores. The response of the optimized architecture to presence of acceptor-like, and donor-like traps in oxide/ channel interface is presented. The acceptor-like traps affect the characteristics in its on-state, whereas the donor-like traps influence the off-state of the device. DIBL reduces with the introduction of interface traps.

Ferroelectric-gate tunnel field-effect transistor one-transistor ternary contents addressable memory

In the era of ‘big data’, the von Neumann architecture has significant energy consumption and latency penalties for data transfer between memory and processor. However, ternary content addressable memories (TCAMs) enable fast and energy-efficient operation by performing a parallel search for given data and returning information about whether it matches. In this study, a single transistor (1T) ferroelectric-gate tunnel FET (FeTFET) was introduced for TCAM operations, and its functionality was verified through technology computer-aided design (TCAD) simulations. The FeTFET has intrinsic directional currents due to its unique p–i–n structure. Also, the transfer curve of the FeTFET can be shifted in both directions depending on the polarization state of the ferroelectric material. By combining these properties of the FeTFET, it was confirmed that stable search operations can be performed for stored logic states. Thus, compared to conventional TCAM cell that use two or more transistors, it is expected that the proposed 1T-TCAM cell can store and search more bits in the same area.

A Compact Model for Single-Event Transient in Fully Depleted Silicon on Insulator MOSFET Considering the Back-Gate Voltage Based on Time-Domain Components

FDSOI (Fully Depleted Silicon On Insulator) devices have a good performance in anti-single-event circuits. However, the bipolar amplification effect becomes a severe problem due to the buried oxide. The previous models for Single Event Transient (SET) of FDSOI did not fully consider the current of all components. Most importantly, they did not take the influence of the back-gate voltage into account. Thus, this paper presents a modeling method for the SET current in FDSOI MOSFET where all three components are modeled individually. The prompt current and diffusion current are modeled with a current source respectively. The Berkeley Short-channel IGFET Model for Silicon-on-Insulator (BSIMSOI) model is integrated into this model to calculate the bipolar amplification current. Compared to using the bipolar transistor model, this method avoids additional current input from the base electrode. It is more consistent with the mechanism of bipolar amplification effect for FDSOI devices without body contact. Instantaneously, an improved model is proposed that considers the influence of the back-gate voltage on the SET of the FDSOI devices. All models are validated through Technology Computer Aided Design (TCAD)simulation results.

Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance

Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.

Non-volatile flash memory based on Van der Waals gate stack using bandgap tunability of hexagonal boron nitride

Electronic devices based on two-dimensional (2D) materials have extended their applications to non-volatile flash memory devices. The gate stack is a key structure in flash memory devices, and the conventional silicon-oxide-nitride-oxide-silicon (SONOS) structure has been widely applied. In this study, we propose a van der Waals (vdW) gate stack based on graphene, molybdenum disulfide (MoS2), and hexagonal boron nitride (hBN) for next-generation flash memory devices. Owing to the bandgap tunability of hBN by functionalization, hBN is capable of forming a tunneling layer, charge trap layer, and blocking layer with different bandgaps, resulting in a suitable energy band offset for program/erase operations and charge storage. This study on the vdW gate stack of MoS2/tunneling hBN/charge trap hBN/blocking hBN/graphene was carried out through technology computer-aided design (TCAD) simulation. The trapped charge density and threshold voltage (Vth) shift were investigated for different bandgaps of the hBN layers. Moreover, the pulse width and cycle were varied to reveal the charge-trapping behavior for further applications.

Effects of polarized-induced doping and graded composition in an advanced multiple quantum well InGaN/GaN UV-LED for enhanced light technology

In this paper, a light-emitting diode in the ultra-violet range (UV-LED) with multiple-quantum wells (MQWs) of InGaN/GaN is designed and analyzed through Technology Computer-Aided Design (TCAD) simulations. The polarization effects in III-nitride heterojunction and the effects of graded composition in the electron blocking layer (EBL) are exploited to enhance the performance of the proposed UV-LED. It is observed that the effect of graded composition in the EBL helps to enhance the electrical and optical performance of the LED, thereby enabling the achievement of some promising results. The simulation-based results demonstrated that superior internal efficiency and an inferior leakage current are achieved by using a graded Al composition in the EBL rather than a uniform composition. The reported results also confirm the remarkable improvement of the light output power by 17% at ∼100 mA when using the graded composition and also show a reduction in series resistance leading to more current. Graded Al composition in the EBL results in the enhancement of electroluminescence spectra (i.e., an increase in the peak of the spectral density).

Recessed Channel Ferroelectric-Gate Field-Effect Transistor Memory With Ferroelectric Layer Between Dual Metal Gates

In this study, we demonstrate a novel recessed channel ferroelectric field-effect transistor (FeFET) with gate metal/ferroelectric (FE) layer/inter-metal (IM)/interlayer (IL)/Si stacks, which can be called as dual metal gates recessed channel FeFET (DM-RFeFET), for nonvolatile memory applications with high performance and robust reliability. Through technology computer-aided design (TCAD) simulations with calibrated FE and device model parameters, it is revealed that the DM-RFeFET can have the wide memory window (MW) and the possibility of endurance improvement by maximizing the area ratio of FE and IL without sacrificing the footprint. Furthermore, the guidelines for the DM-RFeFET design are provided in terms of recess depth and additional high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> blocking layer between IM and IL to maximize the MW and to minimize IM charging by the gate leakage current.

Investigation on Variability of Ferroelectric-Gate Field-Effect Transistor Memory by Random Spatial Distribution of Interface Trap

We investigated the variability of memory window (MW) in ferroelectric-gate field-effect transistor (FeFET) by considering the spatial distribution of the trap density at the ferroelectric layer/interfacial layer (FE/IL) interface. Through technology computer-aided design (TCAD) simulations including calibrated ferroelectric parameters, the variability of ultrathin body (UTB) structured FeFETs by the scaling of IL and channel area was confirmed. It was revealed that the reduction of IL thickness (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IL</sub> ) not only increases mean of MW (μMW) but also decreases standard deviation of MW (σMW). Additionally, by identifying the σMW/μMW sensitivity for the reduction of gate length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> ) and channel width (W), it was indicated that W causes the more serious σMW degradation because short channel effects by L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> scaling mitigate the σMW degradation.

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

The ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on the FeFET with recessed channel (RC-FeFET) is identified. By evaluating electric field (e-field) across interlayer (IL) and memory window (MW), the improvements of program/erase cycling endurance and read current sensing margin (RSM) are verified in the RC-FeMFET. Moreover, considering program voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) and polarization switching time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{\mathrm{ p}}$ </tex-math></inline-formula> ), the guide line of the RC-FeMFET design is provided in terms of e-field across IL and MW for 1T-DRAM applications.

Dependence of Temperature and Back-Gate Bias on Single-Event Upset Induced by Heavy Ion in 0.2-μm DSOI CMOS Technology

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET_th) for a DSOI 6T SRAM cell increases by 12.5&#x0025; with back-gate bias of nMOS reduced from 0 to &#x2212;15 V.

Radiation tolerance comparison of silicon and 4H–SiC Schottky diodes

In this paper, silicon and 4H-silicon carbide (4H–SiC) based Schottky barrier diodes (SBD) have been compared for their radiation hardness capabilities through technology computer aided design (TCAD) simulations, using the non-ionizing energy loss (NIEL) mechanism. Both the devices are modeled for radiation effects after choosing same design points through interplay of drift layer doping and thickness for a fair comparison. Device simulation results show the superior radiation tolerance of 4H–SiC SBDs when compared to silicon devices under proton irradiation. On-state simulations reveal that the performance of Si and 4H–SiC diodes begin to degrade at a 1 MeV proton fluence of ~5 × 1011 and ~7 × 1012 cm−2, respectively. The higher radiation tolerance of 4H–SiC SBDs is also observed in off-state simulations. It is found that the reverse breakdown voltage decreases in silicon, whereas it increases in 4H–SiC devices under the effect of irradiation, mainly due to doping compensation mechanism. These observations validate experimental results available in literature and provide a way forward to use TCAD simulations for studying radiation effects in other devices.

Retention Enhancement in Low Power NOR Flash Array with High-κ-Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide.

For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications.

Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs

Quantum confinement effects tend to diminish gate control over the channel, further degrading the channel electrostatics of short channel Double-Gate (DG) Silicon-on-Insulator (SOI) MOSFETs. In this work, we first design an n-channel Junction-less (JL) DG MOSFET with a channel length (Lg) of 10 nm, where the source/drain doping, determined through Technology Computer-Aided Design (TCAD) simulations, enables better gate control for different channel thicknesses (tch) and oxide thicknesses (tox). The source/drain doping, thus determined, enables JL DG MOSFETs to overcome quantum confinement effects while also achieving key ITRS (International Technology Roadmap for Semiconductors) targets in terms of sub-threshold slope (S) and threshold voltage (Vth). We then introduce a heavily doped symmetric p-type silicon layer at the interface of the channel region with the top/bottom oxide such that the thickness and doping of the p-type layer enable tuning of the threshold voltage. In this partially JL DG MOSFET, by replacing the n-type doped silicon with n-type silicon–germanium (Si0.7Ge0.3) of lower doping, determined through TCAD simulations, we continue to demonstrate excellent channel electrostatics (ITRS targets) at short channel lengths (Lg = 10 nm) over a wide range of channel and oxide thicknesses while also showing enhanced strong inversion channel currents.

Low voltage drop tunnel junctions grown monolithically by MOCVD

Tunnel junction devices grown monolithically by metal organic chemical vapor deposition were optimized for minimization of the tunnel junction voltage drop. Two device structures were studied: an all-GaN homojunction tunnel junction and a graded InGaN heterojunction-based tunnel junction. This work reports a record-low voltage drop in the graded-InGaN heterojunction based tunnel junction device structure achieving a de-embedded tunnel junction voltage drop of 0.17 V at 100 A/cm2. The experimental data were compared with a theoretical model developed through technology computer-aided design (TCAD) simulations that offer a physics-based approach to understanding the key components of the design space, which lead to a more efficient tunnel junction.

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD) simulator. Here, cavity is introduced both at source and drain sides of the fixed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric to increase the capture area of biosensors. Sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) is extracted for both neutral and charged (positive/negative) biomolecules considering cavity is fully filled with different dielectric materials (k). We have reported the sensitivity with the variation in height of nanogap cavity (h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> ) for neutral biomolecules in the cavity. The sensitivity of Ge-source DMDG-TFET is found higher than C-DMDG-TFET due to more conduction at the tunnel junction. Also, the subthreshold swing (SS), transfer characteristics, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of these biosensors are reported for different k and h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> considering neutral/charged biomolecules. The sensitivity of partially filled nanogaps with biomolecules like decreasing, increasing, concave, and convex step profiles are reported for both the biosensors. The dynamic range (DR) of both the biosensors are extracted in presence of positive and negative charged biomolecules. The response time of Ge-source DMDG-TFET is reported at different k. A comparative study of proposed biosensor with other reported work is discussed. Finally, the sensitivity is extracted for DMDG-TFET considering other source material like GaAs, InAs, Si-Ge hetero stacked (HS), GaAs-InAs HS.