Dependence of Temperature and Back-Gate Bias on Single-Event Upset Induced by Heavy Ion in 0.2-μm DSOI CMOS Technology

Abstract

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET_th) for a DSOI 6T SRAM cell increases by 12.5&#x0025; with back-gate bias of nMOS reduced from 0 to &#x2212;15 V.