Negative capacitance partially junction-less FET for hysteresis-free and improved analog performance

Abstract

Given the advantage of high transconductance (g m) at low gate voltages (V gs), seen in junction-less (JL) transistors, it becomes important to incorporate these advantages in conventional bulk MOSFETs which have thus far been used extensively for analog circuit applications. In this work, we propose a partially JL channel in a bulk MOSFET device, which when investigated for a metal-ferroelectric-insulator-semiconductor (MFIS) with negative capacitance field-effect transistor (NCFET) shows superior analog device performance, with improved scalability. Through technology computer aided design (TCAD)-based transient simulations, we identify an optimum and almost constant ferroelectric layer thickness for different gate lengths, which enables hysteresis-free behavior, along with reasonably steep sub-threshold slopes (SS), that meets international roadmap for devices and systems specifications. For this device, we then determine the maximum drain voltage, V ds, which ensures no drain-induced barrier raise effects, based on which improved transconductance generation efficiency (g m/I d), with minimal gate induced drain leakage is shown.