Through Silicon Via Process Research Articles

(Keynote) Technological Challenges and Emerging Device Architectures for Future Semiconductor Micro and Nanoelectronics

Semiconductor technology has known an exponential evolution in the last decades and is fully integrated in our everyday life. According to the Semiconductor Industry association (SIA) the global semiconductor industry sales reaches about US$ 700 billion in 2023, corresponding with a shipment of more than 1.2 trillion components. This necessitates implementation of many novel materials, advanced design concepts and new transistor structures.Increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function, are driving microelectronic research towards 3-nm technologies. A large variety of device architectures such as FinFETs, TFETs, negative capacitance, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, CFET and Forksheet structures are extensively investigated for both logic and analog/RF building blocks enabling System-on-Chip (SoC) applications.In addition to the huge progress achieved in silicon technology, heterogenous integration of Ge and III-V technologies on a silicon platform shows a strong potential, leading towards the on-chip integration of building blocks with different functionality. The fact that both Ge and III-V materials can be selectively grown on Si has strongly triggered the interest in heterogeneous integration.Wide bandgap materials such as GaN offer unique features for RF applications used in base stations for mobile communication, complementing the performance of Si devices suffering from limited output power. These materials can epitaxially be grown on Si substrates. One of the main challenges related to the hetero epitaxy of III-V materials on a Si substrate is the control of extended defects due to the lattice mismatch of the different materials. In recent years, there has been a strong increase in the commercial availability of GaN devices, although for certain applications there is a competition with SiC.Complex and dense SoC applications can be realized by 3D wafer stacking using Through-Silicon-Vias (TSV) for wafer-to-wafer bonding. The 3D integration results in a reduction of the RC product and interconnect length, a smaller form factor and enables vertical partitioning. Main challenges are the TSV process module itself (e.g. Cu via filling, mechanical stress, contamination, keep-out-zone), the wafer thinning and handling and the 3D stacking technology (stacking density, pitch, chip-to-chip interconnect etc.). Very promising results are obtained for monolithic sequential 3D (S3D) processing based on the processing of different tiers on top of each other. Difference can be made between transistor level (n- and pMOS), CMOS level (different standard cells in different tiers) and IP block level for the partitioning. In this way it is e.g. possible to process first CMOS circuits in the Si substrate and then further processing in a III-V layer on top. Benefits are related to an enhanced device density per chip area and a shorter interconnection length. A low cost less scalable tier can be processed on top of an expensive scalable tier as done in the case of logic-memory integration.Major trends in above mentioned process integration approaches are reviewed and technological challenges of some process modules and device structures highlighted.

A novel multi-axis pendulum sandwich structure accelerometer

This paper proposes a new scheme of pendulum accelerometer with sandwich structure. In this scheme, the electrical signal on the mass is connected to the wafer surface through glass isolated through-silicon-via (TSV), so that the basic characteristics of the accelerometer can be obtained by wafer-level testing. Compared with the current commercial device process scheme, the packaging and testing cost of the device can be greatly reduced. The glass-in-silicon (GIS) encapsulation caps on both sides of the device are prepared by glass isolated TSV and GIS reflow process. By designing the shape and size of the silicon electrode area and glass area of the GIS caps, the parasitic capacitance between the pendulum structure and the fixed electrode is reduced. Another advantage of using TSV to extract the electrical signal of the mass is that the Z-axis inertial force can be detected when the pendulum structure is placed perpendicular to the direction of gravity acceleration. In addition, electrodes are grown on the side of the split device, and when the pendulum structure is placed parallel to the direction of gravity acceleration, the inertial force of the XY-axis can be detected. The test shows that when the range of the pendulum accelerometer based on this scheme is ±2 g, the noise density of the accelerometer is 42 μg √Hz−1 (X-axis), 40 μg √Hz−1 (Y-axis) and 27 μg √Hz−1 (Z-axis), and the bias instability is 6.6 μg (X-axis), 7.1 μg (Y-axis) and 6.8 μg (Z-axis), reaching the level of commercial devices.

Research of Vertical via Based on Silicon, Ceramic and Glass.

With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore's Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

Wideband Switchable Sharp-Rejection Filter in Compact 3-D Heterogeneous Integration

A switchable bandstop filter (BSF) bank in 3-D heterogeneous integration is presented in this article for multiband applications. Compared with conventional filter banks, the proposed design features wide bandwidth, sharp skirts, compact size, and high integration. In the proposed BSF, double short-ended coupling lines are introduced to expand the operation bandwidth with sharp rejection. Moreover, to significantly reduce the size of the proposed BSFs, an in-house silicon micromachining process is developed to heterogeneously integrate two stacked BSFs with switches by through-silicon vias (TSVs). To experimentally validate the proposed configuration, a two-channel switchable BSF bank is designed, fabricated, and measured. The measured results show a tuning range of 7.95–12.3 GHz (43%), a maximum bandwidth of 30%, and a sharp stopband rejection of 50 dB. These results agree well with simulation. Moreover, the fabricated prototype is only 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times 8\times $ </tex-math></inline-formula> 1 mm3, whereas a typical industrial counterpart is around <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$86\times 74\times18$ </tex-math></inline-formula> mm3, i.e., the size is significantly reduced to 1‱. To the best of the authors’ knowledge, this is the first demonstration of a wideband switchable sharp-rejection BSF chip fully integrated in the TSV process.

Development of Low Temperature Double Level TSV, Hole and Seal Process for Low Pressure Zero Level MEMS Packaging

Through Silicon Via (TSV) technology is considered one of the key methods to enable heterogeneous integration at the third dimension and realize electrical interconnection between device parts. In that context, different components (MEMS, sensors, circuits etc.) can be electrically integrated in 3D manner, increasing stack density, shrinking footprint, and reducing fabrication costs. At MEMS integration, it is important to explore the packaging method that enables the optimum performance of the active MEMS component and the TSV approach to electrically connect it with the package. Herein, we present our via-last approach to integrate a zero-level packaged MEMS wafer defined by cavity SOI (C-SOI) and CMOS readout circuitry (at thermal budget <400ºC). TSV distribution and fabrication route ensures the electrical connectivity of MEMS inertial sensor and CMOS. Furthermore, a hole is added to the layout scheme and sealed afterwards to ensure low pressure encapsulation in the MEMS cavity.In our previous work related to MEMS fabrication [1], we elaborated the superiority of C-SOI start material over conventional fabrication methods (like vapor HF). In our approach, MEMS cavity structures are realized by patterning dielectrics and the moving parts by employing deep Si etch (DSiE) method (Fig 1 a-c). To enhance the dielectric surface smoothness prior bonding, a complementary HF -based clean applied. This way, bonding requirements (Rq<1nm, Rrange<10nm) are met. CMOS wafer is fabricated with a single layer of Cu damascene process in a dielectric stack to create complementary bonding medium for MEMS wafer. Selected dielectrics at MEMS (thermal oxide) and CMOS (SiCN) can perform better at low temperature fusion bonding due to their moisture blocking capability. Next, fusion bonding at room temperature is carried out using assisted force (60kN) to enhance bonding efficiency and completed by curing the wafer pair at 350˚C.In this paper, we present further work to complete the MEMS zero-level packaging through electrical connections and vacuum seal. Fabrication sequence continues on the backside of the MEMS wafer (Fig 1d-g). First the desired top membrane (cap) thickness of MEMS wafer realized by thinning bulk Si substrate down to 50µm. After SiOx deposition, a double TSV approach is carried out aiming to create the electrical interconnections between the package components, one to reach to the sensor parts in MEMS wafer and one to reach to CMOS. TSV for enabling the connection with sensor parts (12x50μm) is realized by DSiE through the top Si membrane and buried oxide (BOX) landing at Si epi layer of C-SOI. Isolation of this TSV is obtained by conformal liner deposition using SACVD SiOx (350C). Liner opening at the TSV base is assisted by a second non-conformal dielectric deposition to protect the sidewall isolation during resistless directional liner etch back at TSV bottom. Metallization of the via is carried out by sequential PVD barrier (Ta) and seed (Cu) depositions; and the TSV is filled with electroplated Cu. MEMS top surface is then cleared either by CMP or by wet and dry etching of Cu and Ta, respectively. TSV for connecting to CMOS (20x80μm) follows the same processing route with an additional DSiE through all the C-SOI MEMS stack and landing on designated plugs on CMOS. With these two TSV schemes it is ensured to bias and measure the inertial sensor, its driving circuitry, and the zero-level package (Fig. 2a)Once the two TSVs fabrication is completed, hole for the vacuum sealing can be created. First, the top dielectric on surface of MEMS wafer is etched in circular areas of diameter 10μm to define where the venting holes will be created. This is mainly to expose Si surface and reduce possible leakage paths, as well as to increase the adhesion of the deposited metallization to close the hole under vacuum. Small hole (Ø2μm) is defined in the middle of the Si circular area by lithography and etching through the top MEMS membrane (50μm) landing on the cavity of the C-SOI (Fig 1f). Vacuum seal of the zero-level package is finalized with bond pad creation which also seals the hole under vacuum. Al deposition is carried out at high vacuum PVD system; the hole is simultaneously sealed and preserve the same vacuum as the PVD chamber. Along with the chamber vacuum level, the Al thickness and power is also very important to achieve the desired seal Fig.2b.Proposed work enables zero-level MEMS hermetic packaging with integrated CMOS and developed on 200mm wafers.[1] Development of Copper/Dielectric Hybrid Fusion Bonding with Cavity for CMOS compatible Wafer Level Hermetic Packaging, A.Malainou, J.Visker, D.Sabuncuoglu, 21st EPTC, Singapore 2019 Figure 1

Analytical and Measurement-Based Method for Diagnosing the Fault of Channels in TSV-Based 3D ICs

Three-dimensional integrated circuits (3D ICs) based on through silicon via (TSV) technology can effectively solve many bottlenecks in the development of ICs. It has rapidly developed into a key cutting-edge technology representing the medium and long-term sustainable development of microelectronics industry. Process fluctuation causes TSV process defects, resulting in the change of structural parameters of RDL and TSV interconnection structure. Finally, it leads to the degradation of performance parameters and functional failure of 3D interconnection and devices. Aiming at the high-resistance and open-circuited faults of 3D ICs, this paper develops an analysis method based on micro nano machining and detection technology. The electrical characteristics and images of typical chain TSV interconnections are analyzed by scanning electron microscope high-resolution imaging. The mechanism of fault diagnosis is based on potential difference and electron transfer.

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

A RF Redundant TSV Interconnection for High Resistance Si Interposer.

Through Silicon Via (TSV) technology is capable meeting effective, compact, high density, high integration, and high-performance requirements. In high-frequency applications, with the rapid development of 5G and millimeter-wave radar, the TSV interposer will become a competitive choice for radio frequency system-in-package (RF SIP) substrates. This paper presents a redundant TSV interconnect design for high resistivity Si interposers for millimeter-wave applications. To verify its feasibility, a set of test structures capable of working at millimeter waves are designed, which are composed of three pieces of CPW (coplanar waveguide) lines connected by single TSV, dual redundant TSV, and quad redundant TSV interconnects. First, HFSS software is used for modeling and simulation, then, a modified equivalent circuit model is established to analysis the effect of the redundant TSVs on the high-frequency transmission performance to solidify the HFSS based simulation. At the same time, a failure simulation was carried out and results prove that redundant TSV can still work normally at 44 GHz frequency when failure occurs. Using the developed TSV process, the sample is then fabricated and tested. Using L-2L de-embedding method to extract S-parameters of the TSV interconnection. The insertion loss of dual and quad redundant TSVs are 0.19 dB and 0.46 dB at 40 GHz, respectively.

The TSV process in the hybrid pixel detector for the High Energy Photon Source

HEPS-BPIX3 is the third prototype of a single-photon counting pixel detector with 1.4 million pixels developed for applications using synchrotron light sources. It follows the previous prototypes with a pixel size of 150μm×150μm and frame rate up to 1.2 kHz at 20-bit dynamic range. We started to upgrade it with the through silicon via (TSV) process to reduce the insensitive gap between modules. The TSV process drills vias at the pads of the readout chip, and makes connections between the front and back sides. The redistribution layer (RDL) and bump bonding are performed at the bottom of readout chip to connect the control, readout signals and power supplies to the PCB. By using this so-called three-dimensional (3D) integration techniques, the insensitive area of the module is reduced from 26.3% to 11.8%. The assembled modules have been tested with X-ray and synchrotron light source, and the results show that the readout chips work well following the TSV process without any measurable performance degradation.

Design Rules for TSV Membranes

The thermo-mechanical robustness of the bottom edge of an open through silicon via (TSV) is investigated by simulating the most critical step during the TSV process flow. In this step, stress arises due to the different thermal expansion coefficients of the materials forming the TSV. By employing the finite element method, the potential energy release rate of a crack at the TSV edge is calculated. The potential energy release rate, which quantifies the crack driving force, reaches its maximum when the diameter of the metal layers is ${\sim }1.25\times $ and ${\sim }1.5\times $ of the TSV diameter. Furthermore, when the metal diameter is three times the TSV, the crack driving force is reduced by ~50% for both aluminum and copper layers forming the TSV membrane. It was found that the crack tends to propagate perpendicularly to the TSV conductive layer, consistently with experimental observations. Meanwhile, the influence of the TSV membrane on the TSV conductive layer is negligible at distances further than 10% of the TSV height. Results show also that the reduction of 25% of the metal amount of the thickest layer lowers the crack driving force by 40% in comparison to the continuous layer.

A Novel Seedless TSV Process Based on Room Temperature Curing Silver Nanowires ECAs for MEMS Packaging.

The through-silicon-vias (TSVs) process is a vital technology in microelectromechanical systems (MEMS) packaging. The current via filling technique based on copper electroplating has many shortcomings, such as involving multi-step processes, requiring sophisticated equipment, low through-put and probably damaging the MEMS devices susceptible to mechanical polishing. Herein, a room temperature treatable, high-efficient and low-cost seedless TSV process was developed with a one-step filling process by using novel electrically conductive adhesives (ECAs) filled with silver nanowires. The as-prepared ECAs could be fully cured at room temperature and exhibited excellent conductivity due to combining the benefits of both polymethyl methacrylate (PMMA) and silver nanowires. Complete filling of TSVs with the as-prepared 30 wt% silver nanowires ECAs was realized, and the resistivity of a fully filled TSV was as low as 10−3 Ω·cm. Furthermore, the application of such novel TSV filling process could also be extended to a wide range of different substrates, showing great potential in MEMS packaging, flexible microsystems and many other applications.

Advanced through silicon vias for hybrid pixel detector modules

The through-silicon via (TSV) technology offers high-density vertical stacking of integrated circuits, providing a smaller and simpler structure, whilst increasing connectivity and performance. In High-Energy Physics (HEP) experiments, via-last TSVs are exploited to build low material modules for the upgrades of pixel detectors at the High Luminosity LHC (HL-LHC). In order to prove this concept a versatile via-last TSV process is being developed using ATLAS FE-I4 pixel read-out wafers. It allows modules being operated from the chip backside using the TSV-enabled connectivity. The current status of this development is discussed and results of the TSV formation process and the fabrication of the redistribution layer (RDL) on the ATLAS FE-I4 wafers are shown together with electrical results of the first read-out chips while operated via TSVs and RDLs. Another emphasis of this R&D is the industrial benefit, especially for small and medium companies, which will have access to more affordable and, therefore, competitive option.

Pulse Electrodeposition of Cu through-Silicon-Via (TSV) with Surface Suppressor

In recent years, many researches have been focused on the miniaturization of the integrated circuit (IC) feature size to improve the performance of semiconductor devices. However, we are facing the problems such as physical limit of the miniaturization and then increasing processing cost. To overcome these problems the Through-Si-Via (TSV) interconnection, a kind of the 3D interconnection, is a promising technology that could achieve high density, lower energy consumption and high performance in the IC. Since the TSV filling process is costly in the entire TSV process, the TSV filling process which the Cu electrodeposition for TSV is one of key processes. The TSV bottom-up filling which the filling of Cu from the bottom to the top of via with suppressed lateral growth is the solution to ensure a void free filling in high aspect ratio TSV. The bottom-up filling could be achieved by using additives like a suppressor and an accelerator in the electrolyte. In a theoretical model, the suppression breakdown at the bottom of TSV cause the bottom-up filling of TSV. Simultaneous desorption of suppressor by high potential due to ion depletion in the via bottom leads focus of current at the via bottom. Due to adsorption/desorption behavior of the suppressor, the bottom-up TSV filling could be achieved by only using the suppressor.1-3 Furthermore, it was reported that the suppressor at the sidewall is replaced by the accelerator and then the bottom-up filling performance was degraded.3 Lu et al. introduced the nanotwin Cu thin film, which had been attained with pulse electrodeposition.4 Mechanical properties of the Cu thin film is significantly enhanced by highly dense coherent twin boundaries without the degradation of electrical conductivity. Because it could effectively block the dislocation motion without interrupting the migration of electrons.4 The mechanical property of TSV interconnection such as thermal behavior is important as well as the electrical property including electrical conductivity for improvement TSV performance. Therefore, the nanotwin Cu is proper for the TSV interconnection. In this study, nanotwin Cu was applied to fill into high aspect ratio of via (diameter = 5 µm, depth = 60 µm) with pulse current conditions. The deposition condition between direct current and pulse current was compared to observe the filling characteristics. The mechanical properties as the thermal expansion behavior, which is critical to adopting integrated devices, of nanotwin Cu were investigated. As a result, the results with pulse current condition showed obvious improved the TSV filling property than direct current condition. 1. T. P. Moffat and D. Josell, J. Electrochem. Soc., 159, D208 (2012). 2. T. Moffat and D. Josell, Journal of The Electrochemical Society, 159, D208 (2012). 3. L. Yang, A. Radisic, J. Deconinck, and P. M. Vereeckena, J. Electrochem. soc., 160, D3051 (2013). 4. L. Lu, Science, 304, 422-426 (2004).

Progress on TSV technology for Medipix3RX chip

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm; TSV depth: 22 µm; number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance–capacitance–resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

Incorporation of the Organic Additives during the Damascene or TSV Process: Influence of the Applied Waveform

The today increase demand for high-performance microelectronic products requires new reliable interconnection metallization for microelectronic packaging. Copper electroplating is a cost-effective technology, mainly adopted to manufacture interconnects in integrated semiconductor devices [1-3]. In copper 3D interconnections, Damascene or Through Silicon Via (TSV) technologies; numerous factors have an influence on the filling and microstructural results, as the copper bath composition, the applied current density and waveform, the plating cell hydrodynamics…, conditioning the final resistivity of the copper layer. These parameters must be more and more optimised to achieve the filling of a large challenging range via dimensions and very aggressive aspect–ratio. Nevertheless whatever the design of the vias, the substrate composition, the plating cell and other parameters, the free-defect filling of interconnections is obtained only by bottom-up mechanism, where the copper deposition is promoted by superfilling effect and limited on the top, thanks to the addition of two or three organic additives. Without organic additives, only conformal or sub-conformal platings can be grown, causing voids, defects, lack of adherence and poor compactness. The superfilling mechanisms, depending on the additive composition, their relative concentration and the competition between them, are well described and simulated by the curvature-enhanced acceleration accumulation (CEAC) mechanism [4]. Determined first from steady-state measurements, this model permit to predict the evolution of via filling by copper [5], with no information concerning additives incorporation or signature throughout this layer. Indeed, the use of additives introduces also impurities and additives breakdown products during the copper growing. These contaminating agents create defects during the crystallisation like vacancies or dilatation sites of dislocation and limit grain boundary motion and growth during the self-annealing of the copper layer. These phenomena are well deal in the works of Koh et al. [6], and Stangl et al. [7] and particularly well observed with the use of aged bathes. Strangl et al. [7] have demonstrated the incorporation differences between a regular plated copper film and a pulse plated. Favry et al. [5] have also investigated the organic adsorption and inclusion during the copper growing as a function of the additive concentrations or current density. By the combination of electrochemical measurements and SIMS analysis, they have proved an increase of organic inclusion during a regime modification in the plating process. In this present research work, the influence of the applied waveform on the organic additives incorporations is discussed. The work focuses on the organic trace analyses by complementary analysis methods: XPS and SIMS. Firstly, XPS for X-ray photoelectron spectroscopy is a surface (10 nm) sensitive quantitative technique. The resulting spectrum allows the determination of the elementary and chemical composition of the analysed material and the concentration of the different detected elements. The XPS sensitivity is around 0.1 at.%, allowing a chemical cartography of the sample surface composition just after the bath extraction, with the determination of additive adsorptions during an OCP time. Then thanks to an ionic abrasion during the acquisition, a depth analysis is possible, profiling the elements concentration in the bulk material and not only on the surface. Secondly, based on heavy ions bombardment, SIMS for secondary ion mass spectrometry allows a surface composition analysis by sputtering, collecting and mass analysing of ejected secondary ions. This destructive method enables the determination of the elemental, isotopic and molecular composition of a surface or a bulk. The SIMS sensitivity is around 10-4 and 1 at%, but the quantitative analyse is limited. After electrochemical considerations concerning the influence of applied current density waveforms, this research work presents a comparative study of organic incorporations by XPS and SIMS analyses for different copper layers, taking into account the applied waveforms and the bath composition. [1] M. Paunovic at al, Fundamental Considerations in Modern Electroplating 5th edition, edited by M. Schlesinger and M. Paunovic, Wiley edition (2010) [2] M. Datta, Electrochemical processing technologies and their impact in microelectronic packaging in Microelectronic Packaging, edited by M. Datta, T. Osaka and J.W. Schultze, CRC Press edition (2005) [3] J.W. Dini et al, Electrodeposition of copper in Modern Electroplating 5th edition, edited by M. Schlesinger and M. Paunovic, Wiley edition (2010) [4] P.M. Vereecken et al, IBM J. Res. & Dev., 49 1 (2005) [5] E. Favry et al, Electrochimica Acta 53 (2008) 7004-7011 [6] L.T. Koh et al, Microelectronics Journal 33 (2002) 229-234 [7] M. Stangl et al, Microelectronic Engineering 84 (2007) 54-59 Figure 1

Silicon Wafer Integrated Fan-out Technology

The tremendous growth in the mobile handset, tablet, and networking markets has been fueled by consumer demand for increased mobility, functionality, and ease of use. This, in turn, has been driving an increase in functional convergence and 3D integration of IC devices, resulting in the need for more complex and sophisticated packaging techniques. A variety of advanced IC interconnect technologies are addressing this growing need. These include Through Silicon Via (TSV), Chip-on Chip (CoC), and Package-on-Package (PoP) approaches. In particular, emerging Wafer Level Fan-Out (WLFO) technology provides unique and innovative extensions into the 3D packaging realm. Traditional WLFO technologies are limited in design rules and 3D integration capabilities due to the processes and equipment used for circuit patterning. For more aggressive designs, TSV processes must be incorporated, which often times exceed the cost budget and design requirements needed for the device. Consequently, a gap exists between the design capabilities of WLFO and TSV that needs to be addressed. A new, innovative fan-out structure called Silicon Wafer Integrated Fan-out Technology (SWIFT™) packaging incorporates conventional WLFO processes with leading-edge thin film patterning techniques to bridge the gap between TSV and traditional WLFO packages. The SWIFT methodology is designed to provide increased I/O and circuit density within a reduced footprint and profile for single and multi-die applications. The improved design capability of the technology is due, in part, to the fine feature capabilities associated with this new, innovative wafer-level packaging technique. The fine feature capabilities can allow much more aggressive design rules to be applied compared to competing WLFO and laminate-based technologies. In addition, the unique characteristics of the SWIFT process enable the creation of innovative 3D structures that address the need for IC integration in emerging mobile and networking applications. This paper will review the development of the SWIFT technology and its extension into unique 3D structures. In addition, the advantages of SWIFT designs will be reviewed in comparison to current competing packaging technologies. Process information, material characterization, and design simulation data will be presented to show how the SWIFT process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products. SWIFT is a trademark of Amkor Technology, Inc.

High Aspect Ratio through Silicon Via Filling By Nickel-Tungsten Alloy Using Graphene As a Conducting and Barrier Layer

Recently, three-dimensional (3D) chip stacking becomes more and more important because of “More than Moore” story. Through silicon via (TSV) technology is one approach to achieve the target of “more than Moore”. However, the coefficient of thermal expansion (CTE) of copper filled in the TSV may lead to failure of the TSV interconnects because the copper CTE is much higher than that of silicon. The packaging materials with different CTEs will induce large stress at interfaces of materials. To overcome this problem, we choose nickel to substitute copper as a filling material of TSV since the nickel CTE is lower than copper CTE. To further decrease the CTE of the filling material, a few tungsten whose CTE is similar to that of silicon is codeposited during filling plating. Graphene has drawn extensive attention due to its outstanding electrical and thermal properties. In addition, graphene can be used as a barrier layer of copper diffusion. Also, the CTE of graphene is similar to that of silicon. Hence, we use graphene to replace the TiN barrier layer and the copper seed layer, which was used in the traditional TSV process. The filling performance is evaluated by examining vertical cross-sections and top-down cross-section of the filled TSVs by using optical microscope (OM). The Ni-W pillar is examined by scanning electron microscopy (SEM). The thermal reliability of the fully filled TSV is evaluated after a thermal annealing process. The CTE of the filled Ni-W is measured by thermomechanical analysis.

Bottom-up Cu Filling of through-Silicon-Via(TSV) with Single Additive

Downscaling of the Cu interconnection was one of core technologies to enhance the performance of semiconductor devices. However, the shrinkage of Cu interconnection will face the limitation due to the physical limitation of Si based semiconductor device. In order to maintain the development in semiconductor device, the 3D interconnection is emerged, and the through-Si-via(TSV) interconnection is noticed. Large integration, high efficiency and high performance could be realized by composing the 3D integrated circuit with TSV. Furthermore, hetero interconnection between the logic and memory was possible by accepting the TSV technology. The TSV filling process which plating the Cu in the TSV by electrodeposition was one of core process in TSV process due to high cost and difficulty. During the TSV filling process, bottom-up Cu filling which the Cu filled from the bottom of via to the top, should be occurred for avoiding the void formation and decreasing the processing time. In other to achieve the bottom-up filling, various additives were added in the electrolyte. The suppressor inhibited the deposition rate of Cu at the top surface and the sidewall of TSV. The accelerator promoted deposition rate of Cu at the undermost bottom of TSV. Theoretically, the bottom-up filling of TSV was initiated by suppression breakdown at the bottom of TSV.1-3 Simultaneous detachment of suppressor by high potential due to ion depletion at TSV bottom leads focus of current at bottom of TSV. Therefore, bottom-up TSV filling could be achieved by only using the suppressor. Moreover, it was reported that accelerator substitute the suppressor at the sidewall and disturbed the bottom-up filling.3 In this research, the characteristics of suppressor were systematically investigated to achieve the bottom-up Cu filling of TSV with only using the suppressor. The influence of suppressor concentration on the Cu electrodeposition was investigated by observing the CV curves and morphology of Cu deposit. The influence of suppressor concentration and current density on the bottom-up TSV filling had also been observed. Interesting changes in bottom-up TSV filling by changing experimental conditions were delicately analyzed. Finally, the bottom-up TSV filling was achieved with only using the suppressor. This leaded the perfect and fast void free filling of 60 μm deep TSV within 1000 seconds.

Low‐Temperature Deposition of Reactively Sputtered SiNx Films Applicable to TSV Process

SUMMARYIn the through silicon via (TSV) process, which is a key technology for a three‐dimensional large‐scale integration (LSI), particularly in the “via‐last process,” SiNx films of high density are urgently needed for fabrication at low deposition temperatures. However, it is generally known that a SiNx film prepared at low temperatures shows low film density, resulting in poor insulating barrier properties. As a solution to this issue, we propose the use of the SiNx films deposited by reactive sputtering. We can obtain sputtered SiNx films at high density (2.78 to 2.99 g/cm3) in spite of deposition without substrate heating. The 20‐nm‐thick SiNx films passed an experimental check on barrier properties with respect to Cu diffusion upon annealing at 700 °C for 1 h. The films also show good step coverage for a TSV with an aspect ratio of 1.5. The SiNx films prepared by reactive sputtering are a candidate for a good insulating barrier applicable to the via‐last TSV process.