The TSV process in the hybrid pixel detector for the High Energy Photon Source

Abstract

HEPS-BPIX3 is the third prototype of a single-photon counting pixel detector with 1.4 million pixels developed for applications using synchrotron light sources. It follows the previous prototypes with a pixel size of 150μm×150μm and frame rate up to 1.2 kHz at 20-bit dynamic range. We started to upgrade it with the through silicon via (TSV) process to reduce the insensitive gap between modules. The TSV process drills vias at the pads of the readout chip, and makes connections between the front and back sides. The redistribution layer (RDL) and bump bonding are performed at the bottom of readout chip to connect the control, readout signals and power supplies to the PCB. By using this so-called three-dimensional (3D) integration techniques, the insensitive area of the module is reduced from 26.3% to 11.8%. The assembled modules have been tested with X-ray and synchrotron light source, and the results show that the readout chips work well following the TSV process without any measurable performance degradation.