Threshold Voltage Model Research Articles

An Accurate Model of Threshold Voltage and Effect of High-K Material for Fully Depleted Graded Channel DMDG MOSFET

An Accurate Model of Threshold Voltage and Effect of High-K Material for Fully Depleted Graded Channel DMDG MOSFET

Analytic Model of Threshold Voltage (VTH) Recovery in Fully Recessed Gate MOS-Channel HEMT (High Electron Mobility Transistor) after OFF-State Drain Stress

Today, wide bandgap (WBG) GaN semiconductors are considered the future, allowing the improvement of power transistors. The main advantage of GaN is the presence of two-dimensional electron gas (2Deg) typically used as a conduction layer in normally-on and normally-off transistors. Concerning the normally-off family, several solutions are proposed. Among these, one of the most promising is the MIS-Gate technology that features a gate recess architecture allowing the semiconductor to physically cut off the 2Deg and drastically decrease gate–source leakage currents. The Vth relaxation characteristic, after voltage stress, has been investigated. It has been shown that the main impact is due to charges close to the gate dielectric/GaN interface, precisely dwelling within the dielectric or the GaN epitaxy. This work provides an analytical model of the Vth evolution of these MIS-GATE (metal insulator semiconductor gate) transistors fabricated on GaN-silicon substrate. This model allows the extraction of different trap energy levels from a temporary threshold voltage (Vth) shift after 650 V stress. Based on this method, it is possible to identify up to four different trap energy levels. By comparing state of the art methods, we show that these obtained energy levels are well correlated with either magnesium and carbon impurity or Ga and/or N vacancy sites in the GaN epitaxy.

Threshold Voltage and Flat Band Voltage of Normally on Junction Less Field Effect Transistor

Threshold Voltage and Flat band Voltage model of Normally on JLFET is presented in this paper. The threshold voltage is the value of the gate to source voltages at which the depletion width equals to the thickness of the channel. For a normally on JLFET ideally, no current flows above the threshold voltages. Flat band voltage is the value of the gate voltage at which channel is completely neutral. In other word the thickness of depletion layer and accumulation layer is zero at flat band voltage. The model is based on the minimum central and surface potential of the device. The Threshold voltage is determined from the minimum central potential and the flat band voltage is determined by the minimum surface potential. The two models are validated by comparing them with results obtain from TCAD.

Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-<i>k</i> oxide

<abstract> <p>We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO<sub>2</sub>/high-<italic>k</italic> dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-<italic>k</italic> dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-<italic>k</italic> dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-<italic>k</italic> dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-<italic>k</italic> dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO<sub>2</sub>/ZrO<sub>2</sub>, La<sub>2</sub>O<sub>3</sub>, and TiO<sub>2</sub> with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.</p> </abstract>

Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges

Current research endeavor encompasses comprehensive threshold voltage analysis of a Gaussian-doped Dual work function Material (DM) Cylindrical Gate-all-around (CGAA) MOSFET with temperature variance in presence of fixed interface trap charges. Threshold voltage reliability over a wide range of temperature in presence of trap charges and its Gaussian-parameters such as projected range and straggle based dependencies are exhibited. Short channel response of the device has also been considered. Analytical results are corroborated through simulation outputs from Atlas.

Analytical Model for Gate Capacitance and Threshold Voltage in Fin-Shaped GaN HEMTs

Fin-shaped tri-gate structure is an alternative way to achieve positive threshold voltage shift in gallium nitride (GaN)-based high electron mobility transistors (HEMTs). This results from the combined effect of top-gate and side-gate electric fields. In this work, side-gate capacitance of fin-shaped high electron mobility transistor (fin-HEMT) is estimated using conformal mapping technique. Subsequently, a model is developed to estimate the threshold voltage of the device by incorporating this side-gate capacitance in the existing threshold formulation. This model can be included in any existing compact model framework of HEMTs to predict the threshold voltage for fin-shaped devices. The proposed model, being completely physics-based and scalable, is useful to circuit engineers for optimal design.

Modeling of Threshold Voltage and Subthreshold Current of Junctionless Channel-Modulated Dual-Material Double-Gate (JL-CM-DMDG) MOSFETs

Modeling of Threshold Voltage and Subthreshold Current of Junctionless Channel-Modulated Dual-Material Double-Gate (JL-CM-DMDG) MOSFETs

Dual-gate β-Ga2O3 nanomembrane transistors: device operation and analytical modelling

The physical operation and performance of a dual gate β-gallium oxide nanomembrane field effect transistor (NM-FET) with asymmetric top and back gate oxide thicknesses are investigated for different modes of operation. A physics-based device simulator calibrated with experimental data is used for this purpose. Normally-OFF operation of the NM-FET is demonstrated by electrically tuning the top gate threshold voltage with the applied back gate bias. In addition, analytical models of threshold voltage for all the different modes of operation are presented and the proposed models are rigorously validated with simulation results and experimental data. The effect of individual device parameters on the threshold voltage of the normally-OFF NM-FET is further investigated using the analytical model.

A Physics Based Threshold Voltage Modeling of Trigate Junctionless FinFETs Considering Gaussian Doping

A Physics Based Threshold Voltage Modeling of Trigate Junctionless FinFETs Considering Gaussian Doping

Reliability-Aware SPICE Compatible Compact Modeling of IGZO Inverters on a Flexible Substrate

Accurate circuit simulation reflecting physical and electrical stress is of importance in indium gallium zinc oxide (IGZO)-based flexible electronics. In particular, appropriate modeling of threshold voltage (VT) changes in different bias and bending conditions is required for reliability-aware simulation in both device and circuit levels. Here, we present SPICE compatible compact modeling of IGZO transistors and inverters having an atomic layer deposition (ALD) Al2O3 gate insulator on a polyethylene terephthalate (PET) substrate. Specifically, the modeling was performed to predict the behavior of the circuit using stretched exponential function (SEF) in a bending radius of 10 mm and operating voltages ranging between 4 and 8 V. The simulation results of the IGZO circuits matched well with the measured values in various operating conditions. It is expected that the proposed method can be applied to process improvement or circuit design by predicting the direct current (DC) and alternating current (AC) responses of flexible IGZO circuits.

Electrostatic characterization and threshold voltage modeling of inversion type InGaAs gate-all-around MOSFET

This paper presents an analytical investigation of the electrostatic properties of a moderately doped symmetric gate-all-around nanowire MOSFET having InGaAs channel. The model is continuous from depletion to strong inversion regime that circumvents regional approach, thus smoothly capturing the transition of the charge profile in all regions of operation. The evolution of the model is facilitated by the solution of quasi 2-D Poisson equation with appropriate boundary conditions in a square gate-all-around geometry, incorporating fixed oxide charge and interface trap defects. The determination of mobile charge density leads to the capacitance-voltage (CV) characteristics as a function of gate bias. The CV profile is investigated subject to scaling of physical parameters and material properties. Further, a threshold voltage model is presented for a long channel gate-all-around device that utilizes the well-known double derivative method. This model accurately predicts the threshold voltage variation with fin width, oxide thickness and channel doping, highlighting room for further improvement in electrostatics by incorporating high-k dielectric. The excellent match between the model results and TCAD simulation reflects the validity of the proposed model.

Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

The present article deals with the analytical modeling of threshold voltage of an ultra-thin nanotube Junctionless double-gate-all-around (NJL-DGAA) metal-oxide-semiconductor field-effect-transistor (MOSFET). Under the condition of full depletion, the modeling of the surface potential relating to inner and outer gates of the device has been performed by solving three-dimensional Poisson's equation in cylindrical coordinates with appropriate boundary conditions. Corresponding to inner and outer channel potential expressions, the two different threshold voltages of the device are obtained. Moreover, the connection between the source-to-drain subthreshold current and threshold voltage is investigated. The drain-induced-barrier-lowering (DIBL) as an indicator of short-channel effects has been studied. Further, the quantum confinement effects have been explored through quantum mechanical correction in the threshold voltage model. The model outcomes are compared with data extracted from ATLAS™ TCAD simulations, and good acceptances have been observed.

Analytical modelling and simulation of negative capacitance junctionless FinFET considering fringing field effects

Abstract This article proposes an analytical model for channel potential and threshold voltage for negative capacitance junctionless FinFET (NC-JL FinFET). The Poisson's equation has been solved in collaboration with Landau–Khalatnikov equation to obtain analytical model for electrostatic potential distribution, threshold voltage and DIBL. The effect of fringing field on the potential distribution function due to source/drain spacer has also been taken into consideration. The results of proposed models are also validated and compared with simulated results of Sentaurus TCAD device simulator. The effect of various physical parameters like thickness of ferroelectric layer, fin thickness, spacer length, gate dielectric constant etc. on the performance of device has been studied. Further, the performance is also examined for different technology nodes and its (in context of) SCEs.

Analytical modeling of underlap graded channel field effect transistor as a label-free biosensor

Biosensor based on the field-effect transistor (FET) with an underlap region in one side of the gate has high sensitivity and high probability of biomolecules binding. However, the underlap region presence results in lesser gate control over the channel, leading to lower device characteristics control. In this paper, the channel's grading has been employed in FET with an underlap region in the middle of the gate for label-free biosensing application. Surface potential and threshold voltage models are proposed to analyze its effectiveness in sensing DNA and neutral biomolecules. The introduction of DNA in the underlap area causes hybridization, which changes the biosensor's electrical characteristics due to dielectric and charge modulation and is used as a sensing matrix. The results reveal that the proposed biosensor is not only highly sensitive but also yields improved circuit performance. The analytical findings are verified by using TCAD simulation data. This study helps in the design of a new label-free, ultra-small, and highly sensitive biosensor.

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

Three-Dimensional Channel Potential Model of a Triple Gate MOSFET based on Conformal Mapping Technique

In this paper, an analytical channel potential model of an experimental nano-scaled triple gate MOSFET has been developed that is valid in the subthreshold regime. The potential model is derived by applying the Schwarz–Christoffel transformation method and conformal mapping techniques. The model is derived by superposing the influence of top gate on the potential barrier with the 2D potential solution, which is obtained by considering the presence of only two side gates. From that, the threshold voltage model of the device is also evaluated. To validate our model, the result has been compared with numerical simulation data from 3D TCAD Sentaurus that shows good accuracy for channel length (as short as 30 nm) considered for our device.

Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG SE FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions. • Impact of interface Trap Charges (ITCs) on GS-DMIG SE FD SOI MOSFET. • Analytical Modeling of Surface Potential and Threshold Voltage of GS-DMIG SE FD SOI MOSFET. • Analysis of DIBL effect at different ITC Conditions. • Comparative analysis of proposed FD SOI MOSFET in nanoscale regime. • Design and Analysis of 6T-SRAM cell using n-/p-GS-DMIG SE FD SOI with including effects of ITCs.

A Quasi 2-D Electrostatic Potential and Threshold Voltage Model for Junctionless Triple Material Cylindrical Surrounding Gate Si Nanowire Transistor

A mathematical model used for determining the threshold voltage characteristics and electrostatic potential of a Junctionless Triple Material Cylindrical Surrounding Gate Silicon Nanowire Transistor (JLTMCSGSiNWT) is proposed in this research work and is obtained by resolving the poison equation. Three materials with dissimilar metal functions are used in the construction of the device gate structure. Device parameters used to determine the electrical characteristics are also included in the model. Behavior of the device is investigated through its vertical electrical field distribution along the device channel. Higher drain bias conditions leading to DIBL are reduced in the proposed structure by minimal variation of voltages owing to three different gate materials that maintain a steady field distribution along the channel. This model explicitly shows the impact of various criteria like drain bias voltage, gate bias voltage, thickness of the silicon layer, thickness of the oxide layer, and length of the channel on electrostatic potential and the deterioration of threshold voltage. The proposed analytical model is validated with TCAD simulations and it could be further extended to study the advanced electrical characteristics of the JL Triple Material CSG Silicon Nanowire Transistor.

Influence of the Acceptor-Type Trap on the Threshold Voltage of the Short-Channel GaN MOS-HEMT

In this work, the influence of the acceptor-type trap on the threshold voltage and short-channel effect is analyzed and modeled for the short-channel GaN MOS-HEMT. Particularly, the analysis and modeling are carried out with the dependences of the traps' ionization condition on the gate voltage and drain voltage considered. From the calculated results based on the proposed threshold voltage model, it is found that both the interface acceptor-type trap and buffer acceptor-type trap play a vital role in the threshold voltage reduction for the short-channel AlGaN/GaN MOS-HEMT, due to the acceptor-type trap's detrapping effect induced by the drain voltage. The calculated results are well supported by the numerical simulation, which verified the correctness and accuracy of the presented model.

Analytical Model for Threshold Voltage in UTBB SOI MOSFET in Dynamic Threshold Voltage Operation

This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.