Analytical models of threshold voltage and drain induced barrier lowering in junctionless cylindrical surrounding gate (JLCSG) MOSFET using stacked high-<i>k</i> oxide

Abstract

<abstract> <p>We proposed the analytical models to analyze shifts in threshold voltage and drain induced barrier lowering (DIBL) when the stacked SiO<sub>2</sub>/high-<italic>k</italic> dielectric was used as the oxide film of Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFET. As a result of comparing the results of the presented model with those of TCAD, it was a good fit, thus proving the validity of the presented model. It could be found that the threshold voltage increased, but DIBL decreased by these models as the high-<italic>k</italic> dielectric constant increased. However, the shifts of threshold voltage and DIBL significantly decreased as the high-<italic>k</italic> dielectric constant increased. As for the degree of reduction, the channel length had a greater effect than the thickness of the high-<italic>k</italic> dielectric, and the shifts of threshold voltage and DIBL were kept almost constant when the high-<italic>k</italic> dielectric constant was 20 or higher. Therefore, the use of dielectrics such as HfO<sub>2</sub>/ZrO<sub>2</sub>, La<sub>2</sub>O<sub>3</sub>, and TiO<sub>2</sub> with a dielectric constant of 20 or more for stacked oxide will be advantageous in reducing the short channel effect. In conclusion, these models were able to sufficiently analyze the threshold voltage and DIBL.</p> </abstract>