Third-order Intercept Research Articles

A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA

This article presents a 22.6–39.2-GHz reflectionless receiver (RX) capable of reducing the in-band intermodulation and high-order mixing products. Such RX consists of an absorptive IF amplifier, a double-balance passive mixer, and a dual-path noise-canceling low noise amplifier (LNA). The absorptive IF amplifier is utilized to suppress the out-of-band signal reflected back to mixer, which can reduce the intermodulation and high-order mixing products caused by the remixing of the out-of-band signals. Meanwhile, the dual-path noise-canceling LNA is used for achieving low noise figure (NF) in a wide frequency range. To verify the aforementioned principle, a reflectionless RX is implemented and fabricated using a conventional 28-nm CMOS technology. The measurement shows the minimum NF of 3.6 dB and the peak input third-order intercept point (IIP3) of −11.7 dBm. Besides, the proposed RX can support multi-Gb/s, 256-quadratic amplitude modulation (QAM)/1024-QAM modulation signals.

A Reconfigurable Balun-LNA and Tunable Filter With Frequency-Optimized Harmonic Rejection for Sub-GHz and 2.4 GHz IoT Receivers

A CMOS reconfigurable balun-LNA and tunable filter is proposed for sub-GHz and 2.4 GHz IoT applications. The core of the LNA gain stage is composed of two cascaded inverters for the single-to-differential conversion, and the additional inverter is placed in the feedback path for the implementation of the active feedback. In the sub-GHz band, it operates as an active feedback LNA by enabling all inverter stages. At the narrow 2.4 GHz band, it operates as an inductive source degenerated LNA (ISDLNA) with a minimum noise figure (NF) by disabling the inverter in the feedback path. In order to suppress the unwanted local oscillator (LO) harmonic mixing in the sub-GHz band and provide the frequency-optimized harmonic rejection ratio (HRR), a reconfigurable Sallen-Key (SK) filter-based <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4^{\mathbf {th}}$ </tex-math></inline-formula> -order tunable filter is proposed on the basis of the modified super source follower (SSF) with enhanced loop gain. It covers the entire VHF band with a smaller capacitance tuning ratio by switching the polarity of the output of the modified SSF. Compared to previous works, this work provides the largest tuning range from 50 MHz to 700 MHz without splitting individually optimized circuits corresponding to each frequency band and using no external board components. This is the first suggestion of a fully integrated SK filter-based tunable filter to cover VHF/UHF bands through a hardware re-configurability without increasing the tuning ratio of the switched capacitor array, while providing an optimum HRR performance for corresponding operating frequencies in conjunction with harmonic rejection mixer (HRM). In addition, it proposes a hardware efficient re-configurable balun-LNA to operate as a wideband feedback LNA at sub-GHz and a narrowband ISDLNA at 2.4 GHz without the use of external input matching circuits. In the measurement, the proposed front-end achieves an average power gain ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> ) of 25.9 dB, NF of < 4.25 dB, and in-band input-referred third-order intercept point (IIP3) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;\!\!\!-12.8$ </tex-math></inline-formula> dBm over the tuning range from 50 MHz to 700MHz. The proposed tunable filter shows the frequency-optimized HRR from 10 dBc to 26 dBc over the tuning range while greatly reducing a silicon area. At 2.4 GHz band, it shows <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{S}_{{21}}$ </tex-math></inline-formula> of 14.7 dB, NF of 3.2 dB, and in-band IIP3 of −4.5 dBm. The die area of the proposed circuit, excluding I/O PADs and the measurement output buffer, is less than 2.0 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the front-end working at sub-GHz and 2.4 GHz bands is 33.6 mW and 5.1 mW respectively.

Sub-6 GHz Noise-cancelling Balun-LNTA with Dual-band Q-enhanced LC Notch Filter for 5G New Radio Cellular Applications

This paper presents a blocker-tolerant broadband balun-low-noise transconductance amplifier (LNTA) with a high-Q dual-band LC notch filter for 5G new radio (NR) sub-6GHz cellular applications. The proposed balun-LNTA employs a noise-cancelling 1:5 CG-CS balun-LNA topology with local feedback gm-boosting and modified current-bleeding techniques to support entire bands of sub-6 GHz 5G NR application with less than 5 dB NF performance and balanced output of balun-LNTA. The dual-band Q-boosted LC notch filter with a band-switchable differential inductor is also proposed to enhance blocker tolerance of the receiver by removing out-of-band blockers and strong transmitter leakage signals. Simulated in a 65-nm CMOS process, the designed balun-LNTA achieves a minimum noise figure of 2.38 dB, a maximum transconductance gain of 44 mS, an S11 of less than -10 dB over the frequency range of 50 MHz-6 GHz, an input-referred third-order intercept point of 1.82 dBm, and blocker rejection ratios of more than 15 dB. It consumes 5.9 mA from a nominal supply voltage of 1 V. Its active die area is 0.55 mm².

Temperature sensitivity analysis of dual material stack gate oxide source dielectric pocket TFET

The variation of the temperature-dependent performance of an electronic device is one of the major concerns in predicting the actual electrical characteristics of the device as the bandgap of semiconducting material varies with temperature. Therefore, in this article, we investigate impact of temperature variations ranging from 300 to 450K on the DC, analog/ radio frequency, and linearity performance of dual material stack gate oxide-source dielectric pocket-tunnel-field-effect transistor (DMSGO-SDP-TFET). In this regard, a technology computer-aided design simulator is used to analyze DC, and analog/radio-frequency performance parameters, such as carrier concentration, energy band variation, band-to-band tunneling rate, $$I_\mathrm{DS}-V_\mathrm{GS}$$ characteristics, transconductance ( $$g_{m}$$ ), cut off frequency ( $$f_{T}$$ ), gain-bandwidth product, maximum oscillating frequency ( $$f_{\max }$$ ), transconductance frequency product, and transit time ( $$\tau $$ ) considering the impact of temperature variations. Furthermore, linearity parameters, such as third-order transconductance ( $$g_{m3}$$ ), third-order voltage intercept point (VIP3), third-order input-interception point (IIP3), and intermodulation distortion (IMD3) are also analyzed with temperature variations as these performance parameters are significant for linear and analog/radio-frequency applications. Moreover, the performance of the proposed DMSGO-SDP-TFET is compared with the conventional dual-material stack gate oxide-tunnel-field-effect transistor (DMSGO-TFET). From the comparative analysis, in terms of percentage per kelvin, the DMSGO-SDP-TFET demonstrates lesser sensitivity towards temperature variation. Hence, the proposed DMSGO-SDP-TFET is a suitable candidate for low-power switching, and biosensing applications at elevated temperatures as compared to conventional DMSGO-TFETs.

A Wideband Low-Power Balun-LNA with Feedback and Current Reuse Technique

This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise figure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage (gmCG), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage (gmCS) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of −10 dBm while consuming only 5 mW of power from a 1.2 V supply.

A 0.4-V High-Gain Low-Noise Amplifier Using a Variable-Frequency Image-Rejection Technology

A 0.4-V high-gain low-noise amplifier (LNA) using a variable-frequency image-rejection technology in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process has been proposed. By using forward body biasing and folded topology, the supply voltage and power consumption can be reduced. For achieving low power consumption and small chip area, a feedback capacitor is used to shrink the size of the inductors of the input impedance matching. Moreover, a gain-enhancement-and-image-rejection (GEIR) circuit including an inductor and a variable capacitor is proposed for achieving GEIR simultaneously. The image-rejection frequency can be altered for avoiding strong image signals by the variable capacitor. The proposed LNA shows the measured results including a 15-dB power gain, a 2.6-dB noise figure, and a &#x2212;13-dBm input third-order intercept point at 2.4 GHz, respectively. And the measured variable image rejection ratio ranges from 14 to 39 dBc around 3&#x2013;3.6 GHz for avoiding strong image signals. The measured <inline-formula> <tex-math notation="LaTeX">$P_{\text {dc}} $ </tex-math></inline-formula> is 0.8 mW.

Dual-Resistive Feedback Wideband LNA for Noise Cancellation and Robust Linearization

Input-matching, gain, noise figure (NF), linearity, and power consumption are crucial performance metrics that are tightly coupled in a typical low-noise amplifier (LNA). In this article, a self-forward-body-bias (SFBB) inverter-based dual-resistive feedback structure incorporating a linearity feedback-bias scheme with optimal transistor size is proposed to address the performance trade-offs for improving gain, NF, and linearity with minor impacts on other performance characteristics. The proposed structure cancels the noise and nonlinearity of the input stage simultaneously, and partially improves the noise and nonlinearity of the output stage, as shown in theoretical analyses and simulations. In contrast to the conventional linearization technique, the resulting linearity improvement is robust against process, voltage, and temperature variations. Fabricated in a 65 nm triple-well RF complementary MOS (CMOS) process, the proposed LNA achieves a minimum NF of 1.56 dB and power gain of 12.8 dB over a 3 dB bandwidth of 0.02&#x2013;2.6 GHz while consuming 6 mW from a low supply voltage of 0.9 V. The measured input second- and third-order intercept points (IIP2 and IIP3) are 29.5 and 2 dBm at 1 GHz, respectively.

Fast Design Space Exploration and Multi-Objective Optimization of Wide-Band Noise-Canceling LNAs

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be represented by the input-referred third-order intercept (IIP3). In this work, we present a variation-aware automated design and optimization flow for a wide-band noise-canceling LNA. We include the circuit non-linearity in the optimization flow without using a simulator in the loop. By describing the transistors using precomputed lookup tables (LUTs), a design database that contains 200,000 design points is generated in 3 s only without non-linearity computation and 10 s when non-linearity is taken into account. Using a gm/ID-based correct-by-construction design procedure, the generated design points automatically satisfy proper biasing, input matching, and gain matching requirements. The generated database enables the designer to visualize the design space and explore the design trade-offs. Moreover, multi-objective optimization across corners for a given set of specifications is applied to find the Pareto-optimal fronts of the design figures-of-merit. We demonstrate the presented flow using two design examples in a 65 nm process and the results are verified using Cadence Spectre.

Analysis and Design of a Wideband Low-Noise Amplifier with Bias and Parasitic Parameters Derived Wide Bandpass Matching Networks

This paper proposes a 110% relative bandwidth (RBW) low-noise amplifier (LNA) for broadband receivers with flat gain, low noise and high linearity. Bias and parasitic parameters derived wide bandpass (BPDWB) matching networks and a cascode with dual feedbacks are introduced for broadband performance. Matching network design procedures are demonstrated, and results show that the frequency response of the network fits the target impedance well from 1 GHz to 3.5 GHz. The proposed BPDWB network improves the design efficiency and enhances the prediction accuracy of impedance matching. The proposed LNA in 0.25 μm GaAs pseudomorphic high electron mobility transistor (GaAs pHEMT) technology realizes a minimum NF of 0.45 dB at 1.6 GHz where the NF is less than 0.55 dB within the operating frequency band. A flat gain of 22.5–25.2 dB is achieved with the input voltage standing wave ratio (VSWR) below 1.22 and output VSWR less than 2.5. In addition, the proposed LNA has good linearity where the output third-order intercept point (OIP3) is better than +31.5 dBm, and the output 1 dB compression point (OP1dB) is better than +19 dBm over the wide frequency range.

A Wideband E/W-Band Low-Noise Amplifier MMIC in a 70-nm Gate-Length GaN HEMT Technology

This article reports on a gallium-nitride (GaN) low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with a 3-dB gain bandwidth (BW) from 63 to 101 GHz. The MMIC is fabricated in the Fraunhofer IAF 70-nm GaN-on-silicon-carbide (SiC) high-electron-mobility transistor (HEMT) technology. The four-stage common-source LNA exhibits an average noise figure (NF) of 3 dB for a measured frequency range from 75 to 101 GHz. The MMIC reaches a minimum NF of 2.8 dB at an operating frequency of 83 GHz. A mapping of two 100-mm wafers shows an excellent homogeneity with an 86% yield and an average NF of 3–3.3 dB. At 100 GHz, the LNA obtains output-referred 1-dB compression and third-order intercept points of 12.1 and 14.4 dBm, respectively. Furthermore, comprehensive investigations of the bias dependence of all measured performance parameters provide an insight into the presented device and LNA. To the best of the authors’ knowledge, this MMIC demonstrates the lowest NF among GaN LNAs at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}/{W}$ </tex-math></inline-formula> -band frequencies.

A 7–9 GHz I/Q Up-Conversion Mixer Employing a Linear Voltage-to-Current Converting Baseband Input Stage for 5G New Radio Cellular Applications

This work presents a 7–9[Formula: see text]GHz in-phase/quadrature (I/Q) direct up-conversion mixer employing a linear voltage-to-current converting baseband input stage for 5G new radio frequency range 2 cellular applications. The proposed baseband stage improves both the large-signal handling capability and small-signal linearity at the input stage of the mixer. The designed double-balanced I/Q up-conversion mixer, which is based on Gilbert-cell mixer, consists of a voltage-to-current converting input stage, switching stages, and an RLC tank. Simulated in a 40-nm CMOS process, the up-conversion mixer achieves a conversion gain of 5[Formula: see text]dB, input-referred third-order intercept point of 9.6[Formula: see text]dBm, and input 1-dB gain compression point of –0.8[Formula: see text]dBm. It draws a DC bias current of 15.8[Formula: see text]mA from a nominal supply voltage of 1.1[Formula: see text]V, and the active area is 0.129[Formula: see text]mm2.

Fast and Miniaturized Phase Shifter With Excellent Figure of Merit Based on Liquid Crystal and Nanowire-Filled Membrane Technologies

This paper presents a highly miniaturized tuneable microstrip line phase shifter for 5 GHz to 67 GHz. The design takes advantage of the microstrip topology by substituting the ground plane by a metallic-nanowire-filled porous alumina membrane (NaM). This leads to a slow-wave (SW) effect of the transmission line; thus, the transmission line can be physically compact while maintaining its electric length. By applying a liquid crystal (LC) with its anisotropic permittivity as substrate between the transmission line and the NaM, a tuneable microstrip line phase shifter is realized. Three demonstrators are identically fabricated filled with different types of high-performance microwave LCs from three generations (GT3-23001, GT5-26001 and GT7-29001). The measurement results show good matching in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$50\ \Omega$</tex-math></inline-formula> system with reflection less than −10 dB over a wide frequency range. These demonstrators are able to reach a maximum figure of merit (FoM) of 41 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> /dB, 48 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> /dB, and 70 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{\circ }$</tex-math></inline-formula> /dB for different LCs (GT3-23001, GT5-26001 and GT7-29001, respectively). In addition, experiments show that all three LCs should be biased with square wave voltage at approximately 1 kHz to achieve maximum tuneability and response speed. The achieved response times with GT3-23001, GT5-26001 and GT7-29001 are 116 ms, 613 ms, and 125 ms, respectively, which are much faster than other reported LC phase shifter implementations. Large-signal analysis shows that these implementations have high linearity with third-order interception (IP3) points of approximately 60 dBm and a power handling capability of 25 dBm.

A 7.2–27.3 GHz CMOS LNA With 3.51 ±0.21 dB Noise Figure Using Multistage Noise Matching Technique

A wideband low-noise amplifier (LNA) with low and flat noise figure (NF) is presented in this article. For conventional wideband noise matching, the noise performance in the high-frequency region of the entire wideband is usually deteriorated due to the frequency-dependent nature of the minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) for a MOSFET. To address this issue, a novel wideband noise matching approach aiming at noise matching in high band is proposed. This approach can reduce the NF in high band at the cost of a slight NF increase in low band, eventually achieving a low and flat NF and thus a better overall noise performance for a wideband LNA. In addition, the multistage noise matching technique is employed at high frequencies to further reduce the NF caused by the second amplification stage. To validate the proposed techniques, a two-stage LNA prototype was designed and fabricated using a 65 nm CMOS process. The experimental results indicate a peak gain of 16.6 dB with a −3 dB bandwidth (BW) from 7.2 to 27.3 GHz (a fractional BW of 116%). Within the entire band of interest, the simulated NF is low and almost constant (3.3–3.4 dB), while the measured NF falls within the range of 3.30–3.72 dB. Considering the uncertainty of NF measurement, a 0.21 dB NF flatness is one of the best results among the reported millimeter-wave wideband LNAs. The measured third-order input intercept point (IIP3) is −6 dBm at 20 GHz, while the power consumption is 13.2 mW. In addition, only two passive transformers are used in this design, leading to a compact chip core area (0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ).

A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters

In this article, we apply a new clock-phase reuse technique to a discrete-time infinite impulse response (IIR) complex-signaling bandpass filter (BPF). This leads to a deep improvement in filtering, especially the stopband rejection, while maintaining the area, sampling frequency, and the number of clock phases and their pulsewidths. Fabricated in 28-nm CMOS, the proposed BPF is highly tuneable and is capable of achieving a 70-dB stopband rejection at 50-MHz offset with 25% duty-cycle clocks while consuming 1.65 mW. The achieved in/out-of-band third-order intermodulation intercept point (IIP3) is +2.5 dB and +17.3 dBm, respectively, and the input-referred noise (IRN) is 1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm {nV}}/{\sqrt {\mathrm{ Hz}}}$ </tex-math></inline-formula> .

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

This paper presents a bias modulation linearization technique for a 919-923MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm₃) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm² to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (P_out) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear P_out of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.

Design of Second-Order Multifunction Filter IC Based on Current Feedback Amplifiers With Independent Voltage Gain Control

This paper presents the integrated circuit (IC) design and implementation of the voltage-mode (VM) second-order gain-controlled multifunction filter (GMF), which consists of three current feedback amplifiers (CFAs), two grounded capacitors and four resistors. The design and implementation of the chip are based on a 0.18 &#x03BC;m process technology, and offers the attractive advantages of high efficiency, high reliability, low voltage, low power consumption, small size and good performance. The VM-GMF chip implements low-pass (LP), inverting band-pass (IBP) and band-stop (BS) filtering functions, and can independently control the gain of LP, IBP and BS filtering functions. The chip operates with a wide input voltage of 1.2 V_pp at &#x00B1;0.9 V supply voltage, and has a figure-of-merit (FOM) of 66.7%. The on-chip measured input power at 1-dB compression point (IP1dB) is about 7.5 dBm with good linearity and the measured power dissipation (PD) is 5.4 mW with low voltage and low power consumption. The measured phase noise (PN) at an offset frequency of 1 kHz is -100.61 dBc/Hz. The measured value of the third-order intermodulation distortion (IMD3) is -57.38 dBc and the third-order intercept point (TOI) is 21.77 dBm. Simulations and on-chip experimental measurements demonstrate the theoretical analysis of the proposed VM-GMF.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

Temperature dependency and linearity assessment of dual-metal gate stack junctionless accumulation-mode cylindrical surrounding gate (DMGS-JAM-CSG) MOSFET

A physics-based temperature-dependent analytical model for a Dual- Metal Gate Stack Junctionless Accumulation-Mode Cylindrical Surrounding Gate (DMGS-JAM-CSG) MOSFET has been presented in this paper by solving the 2D Poisson’s equation utilizing the suitable boundary conditions. The device performance is examined at various temperatures (T = 100K, 300K and 500K) by observing several parameters like potential, electric field, electron concentration and electron velocity. The obtained outcomes are also contrasted with the outcomes acquired after simulation. Further, the device is also analyzed for its analog performance. Lastly, to check the relevancy of the device for RFIC applications, linearity assessment is performed by evaluating its several figure of merits (FOMs) like second-order and third-order Voltage Intercept Points (VIP2, VIP3), third-order Intercept Input Power (IIP3), third-order Intermodulation Distortion (IMD3) and various higher order transconductances. The obtained results are contrasted with an analogous device and it is discovered that DMGS- JAM- CSG MOSFET device acquires better electrical and linearity characteristics. ATLAS 3D device simulator has been utilized to conduct the simulations.

Recent advancement in the design of mixers for software‐defined radios

The implementation of software-defined radio necessitates a versatile radio frequency (RF) front-end that can support multiple standards in different frequency bands. This article presents the state-of-the-art multiband and wideband mixers in the context of different receiver architectures suitable for software-defined radio (SDR). Wideband and multiband mixer designs reported in the literature are categorized on the basis of their circuit architecture. This study tabulates the results of mixer designs with an emphasis on noise figure (NF), conversion gain (CG), linearity, and image rejection ratio. The best parameters reported in the comparison are 68–84 dB of CG, 3.2 dB of NF, 2.5 mW of power consumption, 12.5 dBm of third-order input intercept point, and 0.015 mm2 of area at different frequencies. The study also discusses the design challenges and techniques to overcome those issues. The article concludes with the summary and prospective developments for SDR architectures.

Experimental Investigation of Performance, Reliability, and Cycle Endurance of Nonvolatile DC–67 GHz Phase-Change RF Switches

This article reports high-performance and reliable phase change material (PCM) germanium telluride (GeTe)-based nonvolatile radio frequency (RF) switches. The highly miniaturized ultrawideband dc to 67 GHz millimeter-wave (mmWave) switches is developed in-house using a custom eight-layer microfabrication process. The switches are fully passivated and do not require any special packaging for integrating heterogeneously with other technologies. They are also amenable to monolithic integration with a wide range of RF devices on a single chip, such as phase shifters, impedance tuners, and attenuators, to name a few. The PCM GeTe-based RF switches are experimentally tested for their RF performance variation across the wafer, performance change at high temperature, high-power handling capability, third-order intercept (TOI) through the two-tone testing setup, and switching speed. The nonvolatile resistance state reliability of the PCM switches is experimentally investigated. The presented RF switches are cycled more than one million times, demonstrating reliable actuation operation with a figure of merit exceeding 14.5 THz. A detailed description of the experimental setup for measuring the switching speed, power handling capability, linearity, reliability, and cycle endurance assessment of the PCM switches is presented. The PCM switches developed are compared with the current state-of-the-art demonstrating a clear improvement in various aspects of the switch’s performance.