Abstract
Input-matching, gain, noise figure (NF), linearity, and power consumption are crucial performance metrics that are tightly coupled in a typical low-noise amplifier (LNA). In this article, a self-forward-body-bias (SFBB) inverter-based dual-resistive feedback structure incorporating a linearity feedback-bias scheme with optimal transistor size is proposed to address the performance trade-offs for improving gain, NF, and linearity with minor impacts on other performance characteristics. The proposed structure cancels the noise and nonlinearity of the input stage simultaneously, and partially improves the noise and nonlinearity of the output stage, as shown in theoretical analyses and simulations. In contrast to the conventional linearization technique, the resulting linearity improvement is robust against process, voltage, and temperature variations. Fabricated in a 65 nm triple-well RF complementary MOS (CMOS) process, the proposed LNA achieves a minimum NF of 1.56 dB and power gain of 12.8 dB over a 3 dB bandwidth of 0.02–2.6 GHz while consuming 6 mW from a low supply voltage of 0.9 V. The measured input second- and third-order intercept points (IIP2 and IIP3) are 29.5 and 2 dBm at 1 GHz, respectively.
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