Fast Design Space Exploration and Multi-Objective Optimization of Wide-Band Noise-Canceling LNAs

Karim Elmeligy,Hesham Omran

doi:10.3390/electronics11050816

Abstract

Design optimization of RF low-noise amplifiers (LNAs) remains a time-consuming and complex process. Iterations are needed to adjust impedance matching, gain, and noise figure (NF) simultaneously. The process can involve more iterations to adjust the non-linear behavior of the circuit which can be represented by the input-referred third-order intercept (IIP3). In this work, we present a variation-aware automated design and optimization flow for a wide-band noise-canceling LNA. We include the circuit non-linearity in the optimization flow without using a simulator in the loop. By describing the transistors using precomputed lookup tables (LUTs), a design database that contains 200,000 design points is generated in 3 s only without non-linearity computation and 10 s when non-linearity is taken into account. Using a gm/ID-based correct-by-construction design procedure, the generated design points automatically satisfy proper biasing, input matching, and gain matching requirements. The generated database enables the designer to visualize the design space and explore the design trade-offs. Moreover, multi-objective optimization across corners for a given set of specifications is applied to find the Pareto-optimal fronts of the design figures-of-merit. We demonstrate the presented flow using two design examples in a 65 nm process and the results are verified using Cadence Spectre.

Highlights

The increased demand on integrated circuits in recent decades has increased the need for fast circuit-design techniques to decrease the design time and the time to market
The work presented in this paper focuses on the design automation and optimization of wide-band low-noise amplifiers (LNAs)
The proposed design flow can be applied to any technology node by generating the lookup tables (LUTs) of the desired technology

Summary

Introduction

The increased demand on integrated circuits in recent decades has increased the need for fast circuit-design techniques to decrease the design time and the time to market. An example is the knowledge-based approach, which attempts to solve an inverse problem, i.e., find the transistor sizing and bias voltages given a set of required design specifications. This approach depends mainly on the experience of the analog designer to make some assumptions and use simplified expressions to relate the specifications to the circuit sizing and biasing. The drawback of this approach is the discrepancy between the synthesized design results and the simulation results due to the assumptions and simplifications used [1,3]. The synthesized design point may not be optimal

Methods

Results

Conclusion