Third-order Intercept Point Research Articles

High-Efficiency Power Amplifier with a Multiharmonic Tuning Network

One high-efficiency power amplifier (PA) with a novel multiharmonic tuning (HT) network is presented. The second and third harmonic impedances are simultaneously controlled with a simple offset double-sided parallel strip line (DSPSL)-based output-matching network. Based on the above strategy, high PA efficiency can be achieved by mapping the fundamental and harmonic impedances to the optimum positions, while PA linearity can be improved through third harmonic suppression. The offset DSPSL is used to realize the transmission lines with extremely high impedance ratio in the multiharmonic trapping circuit. For demonstration, a PA using Cree CGH40010 GaN HEMT is designed with up to third harmonic control. The fabricated PA achieves peak power-added efficiency (PAE) and drain efficiency (DE) of 78.2% and 82.3%, respectively, while delivering 39.2-dBm output power at 1.8 GHz. Besides, the output third-order intercept point (OIP3) of the PA has an improvement of 3 dB.

Extended-source broken gate tunnel FET for improving direct current and analog/radio-frequency performance* *Project supported by the University Natural Science Research Key Project of Anhui Province (Grant No. KJ2020A0075) and Excellent Talents Supported Project of Colleges and Universities (Grant No. gxyq2018048).

The various advantages of extended-source (ES), broken gate (BG), and hetero-gate-dielectric (HGD) technology are blended together for the proposed tunnel field-effect transistor (ESBG TFET) in order to enhance the direct-current and analog/radio-frequency performance. The source of the ESBG TFET is extended into channel for the purpose of increasing the point and line tunneling in the device at the tunneling junction, and then, the on-state current for the ESBG TFET increases. The influence of the source region length on the direct-current and radio-frequency performance parameters of the ESBG TFET is analyzed in detail. The results show that the proposed TFET exhibits a high on-state current to off-state current ratio of 1013, large transconductance of 1200 μS/μm, high cut-off frequency of 72.8 GHz, and high gain bandwidth product of 14.3 GHz. Apart from these parameters, the ESBG TFET also demonstrates high linearity distortion parameters in terms of the second- and third-order voltage intercept points, the third-order input interception point, and the third-order intermodulation distortion. Therefore, the ESBG TFET greatly promotes the application potential of conventional TFETs.

A 0.75 V Sub-mW CMOS LNA employing transmitted signal suppression technique in a full-duplex wireless brain-machine interface transceiver

This paper presents a sub-milliwatt (sub-mW) low-voltage CMOS low-noise amplifier (LNA) that can be utilized in a full-duplex transceiver without using duplexer. The topology of the proposed LNA includes a wideband RLC network to suppress and isolate the receiver from a high-power ultra-wideband transmitted signal. This feature is comparable to other reported LNAs, which are only applicable to a narrowband signal instead of a wideband signal. In addition, the combination of a source-degenerated cascode LNA with an inverter-based LNA in the proposed topology achieves an ultra-low-voltage low-power operation with a 0.75 V bias voltage. Analytical results and the circuit implementation in a 180 nm CMOS technology verify that the proposed LNA presents an noise figure (NF) of less than 3.45 dB over a 200 MHz bandwidth at a carrier frequency of 2.4 GHz. Simulation results also demonstrate a 14 dB gain (S21), less than −11 dB input return loss (S11) and 50 dB transmitted signal attenuation rather than the desired signal. The power consumption is only 980 μW at a 0.75 V supply. The input-referred third-order intercept point (IIP3) is about −8 dBm, and the chip occupies an area of 0.37 mm2.

A 28-GHz High Linearity Up-Conversion Mixer Using Second-Harmonic Injection Technique in 28-nm CMOS Technology

A 28-GHz high linearity active up-conversion mixer using 28-nm CMOS is presented in this letter. To enhance the modulated output power level under high-order modulation with IM3 improvement in the high IF input power region, the second-order intermodulation (IM2) signal injection technique is adopted. The positive third-order intermodulation (IM3) signal is generated by mixing the IM2 signal and IF input signal with transistors in the transconductance stage biasing in triode region. Therefore, by combining these opposite IM3 signal at the output of transconductance stage, the IM3 distortion can be alleviated. Besides, the proposed mixer achieves an IM3 distortion improvement in a wide IF power range. The measurement results demonstrate conversion gain (CG) of −6.4 dB and output 1-dB compression point (OP1 dB) of −2.2 dBm with 19 mW. The two-tone measurement results exhibit 10.2 dBm output third-order intercept point (OIP3). Furthermore, with the modulation measured results using single-carrier 256-QAM signal, the proposed mixer also exhibits a distinguished output power enhancement when the linearizer turns on. To the best of the author’s knowledge, this design is the first demonstration and implemented of an IM2 signal injection technique in millimeter-wave frequency, which also improves the output power level of the high-order modulation measurement.

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

In this research work, we have varied several parameters of a carbon nanotube based tunneling field effect transistor (CNT-TFET) such as the dielectric constant of the gate insulator (κ), channel length, oxide thickness, doping level, and the nature of doping to investigate how the performance of the CNT-TFET is affected. The performance analysis has been done based on the following performance criteria: Subthreshold swing (SS), threshold voltage (VT), and on-current to off-current ratio (Ion/Ioff). In addition, we have also analyzed how linearity and distortion figures of merit such as second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3) are affected by parametric variation. By observing the impact of parametric variation on this large number of performance metrics, a compromise choice of structural parameters is possible depending on the application. Moreover, we have proposed an asymmetric doping design that suppresses the highly undesirable ambipolar behavior in CNT-TFET. In a real-space approach, the simulation study has been carried out using the elegant non-equilibrium Green’s function (NEGF) formalism considering tight-binding Hamiltonian.

Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications

This paper presents an ultra-wideband (UWB) low-noise amplifier (LNA) with extremely flat-high-gain and low-noise figure (NF). In traditional resistive feedback topology, input matching, gain, and NF cannot be balanced. For better performance trade-offs in UWB design, a novel emitter-follower resistive feedback (EFRFB) is introduced, which utilizes a common-collector amplifier followed by a feedback resistor to flatten the gain (the ripple reduced by 2.3 dB) while alleviating the constraints between the gain and input matching. The enhanced gain without restraint by S11 is exactly required for noise reduction technology. Moreover, a peaking inductor and two resistors are adopted to improve bandwidth and output matching, respectively. The proposed LNA is implemented in a 0.18-μm SiGe BiCMOS technology and occupies 0.15 mm2 without pads. Measurements demonstrate that the LNA has a gain of 19.5 dB with ripple < 0.6 dB, a minimum NF of 2.8 dB from 2 to 22 GHz, and an input third-order intercept point (IIP3) of–7.6 dBm at 10 GHz while drawing 10.9 mA from a 3.3 V supply.

A wideband frequency translational resistive feedback receiver resilient to large harmonic blockers

By utilizing frequency translational resistive feedback, a recently proposed blocker current-cancelling wideband receiver (Lenka and Banerjee in IEEE Trans Very Large Scale Integr Syst 27(5): 993–1006, 2019), tolerates 0-dBm blockers beyond 40 MHz offset with little degradation in performance. However, like most wideband receivers, the architecture is far less tolerant to “harmonic blockers”, that is, blockers located at or around precise integer multiples of the local oscillator frequency. This paper presents an enhanced blocker current-cancelling receiver that prevents harmonic blockers from undergoing large gain and thus boosts the receiver’s resilience to such blockers. Implemented in a 22-nm CMOS process, the RX can tolerate up to $$-$$ 1 dBm harmonic blockers. On the other hand, it achieves a 1-dB standard blocker compression point of + 3 dBm and out-of-band third-order input intercept point (OB-IIP3) of + 24 dBm at 40 MHz offset from the LO frequency.

Analytical Synthesis of High-Pass, Band-Pass and Low-Pass Biquadratic Filters and its Quadrature Oscillator Application Using Current-Feedback Operational Amplifiers

In this paper, a method of realizing voltage-mode (VM) non-inverting high-pass filter (HPF), band-pass filter (BPF), low-pass filter (LPF), and inverting low-pass filter (ILPF) transfer functions structure with two grounded capacitors and four resistors through an analytical synthesis method is presented. The synthesis structure of the VM biquadratic filter consists of a voltage proportional block and two voltage lossless integrators based on the use of current feedback operational amplifiers (CFOAs). It is demonstrated that the derived biquadratic filter structure can simultaneously realize VM HPF, BPF and ILPF transfer functions or VM BPF and LPF transfer functions at a high-input impedance terminal. The VM biquadratic filter can independently adjust the resonance angular frequency and quality factor. By slightly modifying the proposed biquadratic filter, a VM quadrature sinusoidal oscillator can be achieved. The proposed biquadratic filter and quadrature oscillator have been simulated by OrCAD PSpice and appropriate hardware has been implemented with AD844-type CFOAs. In order to reduce power consumption, reduce chip area, reduce costs, and improve system integration, integrated VM CFOA-based biquadratic filter circuits and quadrature oscillator circuits are very important. The proposed filter and quadrature oscillator have been further fabricated in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> 1P6M CMOS process technology. The entire chip area is 0.974 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including a filter chip cell and an oscillator chip cell. Under the supply voltage of ±0.9 V, the total power dissipation of the filter chip cell is 5.4 mW, and the figure-of-merit (FOM) of filter chip cell is 66.7%. The measured value of the third-order intermodulation distortion of the filter chip cell is −55.29 dBc and the third-order intercept point is 19.9 dBm. The measured phase noise of CFOA-based filter chip cell at 1 kHz offset is less than −99.76 dBc/Hz.

Inductorless Multi-Mode RF-CMOS Low Noise Amplifier Dedicated to Ultra Low Power Applications

This work presents and analyses the design of a multi-mode Low Noise Amplifier (LNA) dedicated to 2.4 GHz Wireless Sensor Network (WSN) applications. The proposed inductorless LNA, implemented in a 28 nm FDSOI CMOS technology, is based on a common-gate configuration imbedded with a common-source stage to boost the overall transconductance of the circuit. The LNA is specifically designed, and optimized, to address three modes of operation. The reconfiguration is performed through current tuning, combined with switching the back gate of the amplification transistors. The proposed implementation allows the figure of merit (FOM) to be maintained constant in the different modes of operation. In the low power mode, the LNA only consumes 350 uW. It achieves a voltage gain (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> ) of 16.8 dB and a noise figure (NF) of 6.6 dB. In the medium performance mode, the gain and the NF are respectively improved to 19.4 dB and 5.4 dB, the power consumption is 0.9 mW. In the high-performance mode, the gain is maximum, 22.9 dB, and the noise figure is minimum, 3.6 dB, for a power consumption of 2 mW. The linearity represented by the input referred third-order intercept point (IIP3) is constant, close to -16 dBm. The reported LNA occupies only 0.0015 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 0.2~3.8-GHz Full-Duplex Receiver With More Than 25 dB Self-Interference Cancellation Using a C-DAC-Based Vector Canceller

This paper presents a $0.2\sim 3.8$ -GHz in-band (IB) full-duplex (FD) mixer-first receiver based on a vector self-interference (SI) canceller. To ensure the wideband orthogonality of the reconstructed SI signal while minimizing the noise figure (NF) degradation in FD mode, a low insertion loss two-stage polyphase filter (PPF) with a lacking resistance and capacitance (LRC) structure is used in the SI canceller. A 6-bits passive capacitor digital to analog converter (C-DAC) attenuator not only realizes the high-precision amplitude adjustment of the reconstructed SI signal but also avoids the linearity limitation of the back-end modules of the canceller and reduces the noise contribution of the front-end modules at the canceller output. A four-phase mixer-first receiver with enhanced out-of-band (OOB) interference suppression is designed to provide sufficient linearity to reduce the SI-induced nonlinear distortion. As a proof of concept, a prototype FD receiver is fabricated in CMOS 65 nm technology and measured in chip-on-board (COB) package. Measurement results show that it can operate in the frequency range of $0.2\sim 3.8$ -GHz with more than 25 dB SIC amount for 10 MHz bandwidth (BW) 64-QAM modulated signals in fixed (30 dB) channel attenuation test setup. The receiver achieves OOB input-referred third-order intercept point (OOB-IIP3) of +24 dBm and OOB input-referred second-order intercept point (OOB-IIP2) of +82 dBm at 1-GHz local oscillator (LO) frequency. In FD mode, the NF degradation is $\leqslant 1.5$ dB. The effective IB-IIP3 and effective IB-IIP2 are enhanced by 15 dB and 28 dB, respectively. The power consumption of entire FD receiver including the SI canceller is less than 44 mW. The active chip area is 0.55 mm2.

2.4 GHz BLE Receiver With Power-Efficient Quadrature RF-to-Baseband-Current-Reuse Architecture for Low-Power IoT Applications

In this paper, a 2.4 GHz Bluetooth low energy receiver employing a power-efficient quadrature RF-to-baseband-current-reuse architecture is presented for low-power low-voltage internet of things applications. The proposed quadrature RF-to-baseband-current-reuse RF front-end consists of a low-noise transconductance amplifier, an active-type polyphase filter-based quadrature generator, transimpedance amplifiers, and double-balanced current-mode passive mixers on a single dc current path. An input matching network is used to perform power-constrained simultaneous noise and input power matching and 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> noise reduction in the RF and baseband domains, respectively. The quadrature RF signals are provided to the single-quadrature mixers through an embedded active-type polyphase filter-based quadrature generator. The implemented Bluetooth low energy receiver is composed of the RF-to-baseband-current-reuse RF front-end, IF amplifiers, two-stage passive- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> polyphase filter, and fifth-order Chebyshev-II <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$G_{m}$ </tex-math></inline-formula> <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-C</i> filters. The proposed design was fabricated using a 65-nm CMOS process and characterized primarily in the Bluetooth low energy operating frequency bands. The active die area of the implemented receiver was 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the receiver drew a bias current of 1.41 mA from a nominal supply voltage of 0.8 V. The Bluetooth low energy receiver achieved a noise figure of 13.2 dB, conversion gain of 42 dB, image rejection ratio of more than 30 dB, and input-referred third-order intercept point of −25 dBm.

Large-Signal Linearity and High-Frequency Noise of Passivated AlGaN/GaN High-Electron Mobility Transistors.

This study proposes AlGaN/GaN/silicon high-electron mobility transistors (HEMTs) grown by a metallorganic chemical vapor deposition (MOCVD) system. The large-signal linearity and high-frequency noise of HEMTs without and with different passivation layers are compared. The experimental data show that the addition of a TiO2 passivation layer to undoped AlGaN/GaN HEMT’s increases the value of the third-order intercept point (OIP3) by up to 70% at 2.4 GHz. Furthermore, the minimum noise figure (NFmin) of the HEMT with TiO2 passivation is significantly reduced.

A Distributed Low-Noise Amplifier for Broadband Linearization of a Silicon Photonic Mach–Zehnder Modulator

RF photonic components suffer from poor spurious-free dynamic range (SFDR) due to the high noise and distortion generated by a silicon photonic (SiP) Mach-Zehnder modulator (MZM). This work demonstrates a distributed silicon-germanium (SiGe) heterojunction bipolar transistor (HBT)-based low-noise amplifier (LNA) co-designed for linearization with a SiP MZM for a broadband radio-over-fiber (RoF) link. The SiGe LNA incorporates a distributed, tunable predistortion scheme that is inherently wideband and improves the third-order intercept point over an 18-GHz range. The assembled SiGe LNA and SiP MZM prototype demonstrates an SFDR as high as 120 dB· Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2/3</sup> at 9 GHz, a 14-dB improvement over previous SiP RF components or RoF links.

High-Gain Ka-Band Analog Photonic Link Using High-Power Photodiode at 1064 nm

We report high-gain, low-noise-figure, and high linearity analog photonic links at 1064 nm using InP/InGaAs modified uni-traveling-carrier (MUTC) photodiodes. Balanced photodiodes reach output powers of 17.7 dBm, 19.8 dBm, 20.7 dBm, and 22 dBm at 38 GHz, 29 GHz, 27 GHz, and 24.5 GHz, respectively. High common-mode rejection ratio (CMRR) of 25 dB and good linearity with a third-order intercept point (OIP3) of up to 34 dBm were measured at 38 GHz for 10-μm-diameter balanced photodiodes. We demonstrate two analog photonic links with different noise reduction techniques without electronic amplification. In the first link, we use balanced detection with a quadrature-biased Mach–Zehnder modulator (MZM) for noise cancellation. Link gain of 6.8 dB, noise figure (NF) of 25.8 dB and spurious free dynamic range (SFDR3) of 114 dB·Hz2/3 at 38 GHz were achieved. The second link works at low bias modulation for improved signal-to-noise ratio with a single photodetector. Record-high gain (19.3 dB at 26 GHz and 17 dB at 38 GHz) and low noise figure (14.5 dB at 26 GHz and 17 dB at 38 GHz) were demonstrated.

Experimental insight into the third‐order intercepts and nonlinear distortion of GaN HEMTs

This research is about investigating the third-order intercept point (TOI) and nonlinear distortion level (NDL) for two GaN HEMTs of different gate lengths with temperature and frequency. As a multi-biasing, input power, frequency and temperature-dependent term; the TOI point and as well as the nonlinear distortion level are particular figures merit relevant to the third-order intermodulation distortion (IMD3) product. The primary results are the output referenced TOI reduced whereas the input referenced TOI raised as the frequency goes higher and the lower gated device exhibits a bit greater magnitude. Over the temperature range measured; the magnitude of TOI and nonlinear distortion considerably changed in accordance to the performance of third order intermodulation distortion (IMD3) component. This investigation of TOI is used to determine what extent distortion is generated, and comparing that to the entryway of the antenna provides a clear strategy for determining if the spec can be met or not. However, distortion level investigation is a critical point to choose the best biasing preference with the device's inlet measurements to establish a solution that fits with the intended usage.

A wideband low power merged balance-balun-LNA and I/Q-mixer

This paper presents a low power wideband RF receiver front-end in CMOS 180 ​nm technology that operates between 0.3 and 4.7 ​GHz. The mixer has a quadrature current commutating gilbert cell configuration that utilizes a novel broadband noise-canceling balanced balun-LNA as the transconductance stage. The noise-canceling balun LNA utilizes an additional noise-reduction technique that enhances its performance noticeably. Both of the common gate and common source stages of balun LNA are matched by employing equal-sized transistors that are biased with the same currents and load resistances. This technique results in superior symmetry, enhanced noise, and linearity performance under reduced power consumption. Post-layout simulation results show that the implemented balun LNA-I/Q-mixer has a conversion gain of 14.05 ​dB. The second and third-order intermodulation intercept points are +42.13 dBm and +4.13 dBm, respectively. The double-sideband NF is 4.74 ​dB. The proposed structure consumes only 6.7 ​mW from a 1.8 ​V supply and occupies a 0.056 ​mm2 chip area.

5th-Order Continuous-Time Low-Pass Filter Achieving 56 MHz Bandwidth 30.5 dBm IIP3 With a Novel Low-Distortion Amplifier

This brief presents a highly linear and high-speed operational amplifier that consists of a double-recycling folded cascode input stage and an adaptive biasing with a flipped voltage follower to boost slew-rate and unity-gain frequency. In addition, frequency compensation is performed by an input cross-coupled phase-lead passive compensation scheme and hybrid Miller-cascode compensation. A 56 MHz -3 dB bandwidth fifth-order programmable gain continuous-time active low pass filter is fabricated in 180 nm CMOS to validate the proposed scheme. The filter achieves 30.5 dBm of third-order interception point at 38 MHz and occupies 0.215 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The filter consumes 14.7 mW with 1.8 V supply and has 0.2 dB in-band ripple.

A Dual-Band Transformer-Coupled Notch Filter Mixer for 2.45-/5.2-GHz WLAN Application

This paper presents a dual-band down-conversion mixer with image rejection feature using transformer-coupled notch filter for 2.45-/5.2-GHz WLAN application. A single center-tapped transformer is integrated to form two differential series inductor–capacitor (LC) resonators as a filter circuit to create attenuation at the image frequencies in eliminating the signal distortion caused by the image signals. Furthermore, an NMOS cross-coupled pair was adopted in the notch filter to improve the image rejection capability due to the presence of negative resistance. Simulated on a standard 130nm CMOS process, the proposed transformer-coupled notch filter mixer achieves a conversion gain of 15.3/10.7 dB, input-referred third-order interception point (IIP3) of − 6.8/− 2.0 dBm and a noise figure of 8.8/14.8 dB for an input RF of 2.45/5.2 GHz with an IF of 500 MHz. The notch filter mixer consumes 5.5 mW of power from a supply voltage of 1.2 V.

A Reconfigurable Passive Mixer-Based Sub-GHz Receiver Front-End for Fast Spectrum Sensing Functionality

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies, the proposed receiver scans multiple frequency bands quickly through mode change of the reconfigurable mixer. The LO generation circuit employs a voltage subtractor-based phase adder and provides highly accurate 25% duty-cycle octet-phase LO signals. The front-end implements a high LO harmonic rejection ratio (HRR) in order to avoid signal corruption by LO harmonic mixing during spectrum sensing. In experiments, the proposed receiver achieves <; 40.3 dB conversion gain, <; 6.6 dB noise figure (NF), > -35.8 dBm in-band input-referred third-order intercept point (IIP3), > -22.3 dBm out-of-band IIP3, and an average 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> LO HRR of 43 dB over 300-800 MHz in DBM&HR mode. Over 600-1200 MHz in SHM mode, it shows >31.8 dB conversion gain, <; 10.4 dB NF, > -30.9 dBm in-band IIP3, and > -20.1 dBm out-of-band IIP3. The switching time between DBH&HR and SHM modes is approximately 135 ns. The power dissipation is 24.7 mW from a 1.2 V supply voltage.

Breaking the Performance Tradeoffs in N-Path Mixer-First Receivers Using a Second-Order Baseband Noise-Canceling TIA

Input-match, noise figure (NF), in-band (IB) third-order input-referred intercept point (IIP3), out-of-band (OB) IIP3, and power consumption are five crucial performance metrics of a radio frequency (RF) receiver. In a typical passive mixer-first receiver, these five performance metrics are tightly coupled with each other. In this article, a second-order baseband noise-canceling (NC) scheme is proposed to break the performance tradeoffs in an N-path mixer-first receiver. Analytical expressions for input impedance, NF, IB-IIP3, and OB-IIP3 of the proposed NC receiver are derived and verified. A prototype mixer-first receiver is implemented in CMOS 180 nm technology and tested in the laboratory. In measurements, the receiver achieves an NF less than 4 dB and IB-IIP3 of +14.5 dBm over a frequency range of 0.2–1.2 GHz. The measured OB-IIP3 is +25 dBm at a frequency offset of 2.2 times the bandwidth while consuming a static power of 20 mW.