Thin Buried Oxide Research Articles

Silicon‐on‐insulator MOSFETs models in analog/RF domain

SUMMARYSeveral physical phenomena specific to silicon‐on‐insulator metal–oxide–semiconductor field‐effect transistors, such as floating body effects, self‐heating, and substrate coupling, are described and modeled. Small‐signal equivalent circuit of ultra‐thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal–oxide–semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band. © (2013) The Authors. INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Published by John Wiley & Sons, Ltd.

MONTE-CARLO SIMULATION OF ULTRA-THIN FILM SILICON-ON-INSULATOR MOSFETs

State-of-the-Art devices are approaching to the performance limit of traditional MOSFET as the critical dimensions are shrunk. Ultrathin fully depleted Silicon-on-Insulator transistors and multi-gate devices based on SOI technology are the best candidates to become a standard solution to overcome the problems arising from such aggressive scaling. Moreover, the flexibility of SOI wafers and processes allows the use of different channel materials, substrate orientations and layer thicknesses to enhance the performance of CMOS circuits. From the point of view of simulation, these devices pose a significant challenge. Simulations tools have to include quantum effects in the whole structure to correctly describe the behavior of these devices. The Multi-Subband Monte Carlo (MSB-MC) approach constitutes today's most accurate method for the study of nanodevices with important applications to SOI devices. After reviewing the main basis of MSB-MC method, we have applied it to answer important questions which remain open regarding ultimate SOI devices. In the first part of the chapter we present a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin fully depleted SOI devices using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on short channel effects (SCEs). The simulations show that the main limiting factor for downscaling is the DIBL and the UTBOX+GP configuration is the only valid one to downscale SGSOI transistors beyond 20 nm channel length keeping the silicon slab thickness above the theoretical limit of 5 nm, where thickness variability and mobility reduction would play an important role. In the second part, we have used the multisubband Ensemble Monte Carlo simulator to study the electron transport in ultrashort DGSOI devices with different confinement and transport directions. Our simulation results show that transport effective mass, and subband redistribution are the main factors that affect drift and scattering processes and, therefore, the general performance of DGSOI devices when orientation is changed

Formation of III–V-on-insulator structures on Si by direct wafer bonding

We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O2 plasma-assisted DWB process with ECR sputtered SiO2 BOX layers and a DWB process based on atomic-layer-deposition Al2O3 (ALD-Al2O3) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO2 and ALD-Al2O3 BOX layers are desorption of Ar and H2O gas, respectively. In order to suppress micro-void generation in the ECR-SiO2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al2O3 BOX layers to increase the deposition temperature of the ALD-Al2O3 BOX layers. It is also another possible solution to deposit ALD-Al2O3 BOX layers on thermally oxidized SiO2 layers, which can absorb the desorption gas from ALD-Al2O3 BOX layers.

Impact of back-gate biasing on effective field and mobility in ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect-transistors

We discuss the role of back-gate biasing on effective field (Eeff) and its impact on the mobility in advanced ultrathin semiconductor-on-insulator metal-oxide-semiconductor field-effect-transistors using the multibranch mobility analysis. This technique is enabled using the integral definition for Eeff, which is the accurate method to determine Eeff even in volume-conduction regime. For further clarification, the difference between Eeff estimated by this integral definition and by the conventional formula is examined for our target devices. From the multibranch mobility analysis, we show that in devices with thin-buried oxide and ground plane doping, the reduction in Eeff due to back-gate biasing is large, leading to a significant mobility enhancement for both N-channel and P-channel devices. Furthermore, we show that the mobility enhancement effect via back-gate biasing in P-channel devices is larger than that in N-channel devices. This enhancement is attributed to the increase in the mobility under the volume-conduction regime. The mobility dependence with respect to Eeff reveals that strong volume conduction is achieved in P-channel devices, leading to a reduction of the surface scattering events at both interfaces, thereby increasing the mobility. This advantage adds to the already reported increase in the population of the light-hole bands.

On the extension of ET-FDSOI roadmap for 22 nm node and beyond

With the current scenario of different candidates to lead the road to 14nm node and beyond, this work presents a thorough Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the scaling possibilities of Extremely Thin Silicon on Insulator technology (ETSOI) considering the impact of Buried Oxide (BOX) engineering on the electrostatic integrity of devices addressed for the forthcoming technological nodes. The simulations show that the combined use of Ultra Thin BOX (UTBOX) and Ground Plane/Back Bias (GP/BB) plane are enabling techniques to ensure an adequate control of Short Channel Effects (SCEs) in order to extend the roadmap of ETSOI technology down to 11nm node and beyond. BOX engineering also makes possible a redefinition of standard scaling rules relaxing the constraints on LG/TSi ratio with the advantage over Multiple Gate FETs (MuGFETs) based architectures of a fully compatible fabrication process with main stream planar technologies.

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.

Back-Gate Bias Dependence of the Statistical Variability of FDSOI MOSFETs With Thin BOX

The impact of back-gate bias on the statistical variability (SV) of FDSOI MOSFETs with thin buried oxide (BOX) is studied via 3-D “atomistic” drift-diffusion simulation. The impact of the principal sources of SV, i.e., random dopant fluctuations, line edge roughness, and metal gate granularity, on threshold voltage, drain-induced barrier lowering, and drive current is studied in detail. It is shown that reverse back-bias is beneficial in terms of reducing the dispersion of the off-current and the corresponding standby leakage power, whereas forward back-bias reduces the on -current variability. The correlation coefficients between relevant figures of merit and their trends against back-bias are also studied in detail, providing guidelines for the development of statistical compact models of thin-BOX FDSOI MOSFETs for low-standby-power circuit applications.

UTBOX SOI Substrate with Composite Insulating Layer

Ultra thin body and Buried Oxide (BOX) SOI substrates are of high interest for the fabrication of high performance CMOS Fully Depleted (FD) devices. We have investigated the fabrication of SOI wafers with an Ultra Thin alumina BOX (UTBOX). 300 mm SOI substrates with composite SiO2 / Alumina / SiO2 buried insulating layer have been manufactured using industrial Smart CutTM technology and a BOX dissolution stage. The substrates quality is in line with standard UTBOX products in terms of layers morphology, defectivity and thickness uniformity. It is shown that the thin SiO2 capping layers prevent the collapse of the alumina layer at high temperature and bring excellent BOX/silicon interface electrical quality with low DIT and good carrier mobility. The alumina layer exhibits a stable embedded negative charge of 3 × 1012 cm−2 and a low EOT according to its high permittivity. These unique properties make composite BOX substrates especially interesting for charge trapping applications or in FD devices manufacturing where alumina can act as an embedded etch stop layer.

SOI high‐voltage LDMOS with novel triple‐layer top silicon based on thin BOX

A novel SOI high-voltage LDMOS with a triple-layer top silicon (TLTS) is investigated. The top silicon layer of the TLTS LDMOS consists of n− silicon with a p-top layer, p− silicon in the middle, and n+ silicon on the interface. On the condition of high-voltage blocking state, the electric fields of the drift region and BOX are modulated and optimised by the triple-layer top silicon, respectively, which induces a high BV of 624 V for the TLTS LDMOS with a thin buried oxide layer (BOX) of 0.4 µm. Compared with several SOI devices, the proposed TLTS LDMOS has a higher figure-of-merit.

Thermal Conductivity of SOI LDMOS Device

In this paper, the thermal conductivity of lateral double diffused metal oxide semiconductor (LDMOS) was studied. In order to optimize their properties, the LDMOS device based on the lower surface of field (RESURF) theory join the second field plate technology. Power device self-heating effect will affect the carrier mobility, making its negative resistance effect in IV characteristic curve under the high-power condition. As the thermal conductivity of SiO2 is low, the self-heating effect of SOI device is more obvious. The simulation using Silvaco -TCAD software for different buried oxide (BOX) with different SOI layer thickness accordingly show that the thicker SOI layer and the thinner buried oxide layer, the smaller the self-heating effect.

Analysis of the Self-Heating Effect in UTBOX Devices

This work presents a study of the self-heating effect (SHE) on –n type UTBOX devices. Thinner buried oxide indicated a reduction on degradation caused by the SH phenomenon as shown by drain current and transient time. Addressed to that, a smaller output conductance variation with the frequency was also related where a higher frequency is required for the SHE emergence. The ground plane region was also considered on the UTBOX devices indicating to be favorable in suppress the SHE.

Investigation and Integration of Polycrystalline Silicon/TiN/SiON Gate Stack in Silicon on Thin Buried Oxide Complementary Metal Oxide Semiconductor Field Effect Transistors

We developed fully depleted silicon on thin buried oxide (SOTB) complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a polycrystalline-silicon (poly-Si)/TiN/SiON gate stack. We investigated the flat-band voltage (Vfb) shift of the gate stack for the threshold voltage (Vth) symmetry of SOTB CMOSFETs. We found that the Vfb shift depended on both TiN thickness and thermal load. Thicker TiN above 15 nm is preferable for obtaining the midgap value of Vfb with considering the thermal budget of the SOTB process. We also integrated the gate stack into SOTB CMOSFETs, which showed that the Vth roll-off characteristics corresponded to the proper control of the effective work function by considering how the impurity-related work function modulation affects. Narrow channel characteristics of the TiN-gate SOTB CMOSFETs were also shown to be superior to fully silicided gate SOTB devices due to the less silicidation.

Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs With Thin BOX

Carrier mobility (μ) at various back-gate biases is studied for nand p-channel ultrathin (8 nm) SOI MOSFETs with thin (10 nm) buried oxide (BOX) and ground plane (GP). We found that μ did not deteriorate for either thin BOX or GP structure, even in the back channel (BC). We also found the largest μ enhancement effect in p-channel devices by the back-gate bias. As this enhancement effect could conceal the superior μ at the Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, μ was maximized when both the front channel and BC were conducting. By contrast, μ in n-channel devices was maximized only when the BC was activated. This large μ gain in p-channel devices is promising for further CMOS scaling.

Reaching sub-32 nm nodes: ET-FDSOI and BOX optimization

This work presents a thorough study of the impact of different Buried OXide (BOX) configurations on the scaling of extremely thin SOI devices (ET-FDSOI, also known as UTSOI) to sub-32nm nodes using a Multi-Subband Ensemble Monte Carlo simulator (MS-EMC). Standard thick BOX, ultra thin BOX (UTBOX) and UTBOX with ground plane (UTBOX+GP) solutions have been considered in order to check their influence on Short Channel Effects (SCEs). Simulations show that for channel lengths shorter than 20nm, silicon thickness thinner than 5nm are needed to control Drain Induced Barrier Lowering (DIBL) below 100mV/V. However, thickness variability and mobility reduction could play an important role for so small thickness. Nevertheless, we show that with the appropriate combination of UTBOX and GP it is possible to use thicker Si layers, even for channels shorter than 20nm, and keeping SCEs under control, i.e., DIBL below 100mV/V.

Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs

This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL.

Polycrystalline Silicon Layers with Enhanced Thermal Stability

We report on a new method of external gettering in silicon substrate for semiconductor applications. The proposed method is based on the deposition of a multilayer system formed by introducing a number of thin buried silicon oxide layers into the thick polycrystalline silicon layer deposited on the wafer backside. Oxide films of a few nanometer thicknesses significantly retard both the grain growth and subsequent loss of the gettering capability of the polycrystalline silicon layer during high temperature annealing. The mechanisms of the grain growth and the influence of the embedded oxide layers on the gettering function in the multilayer system are discussed. We used scanning electron microscopy and transmission electron microscopy for the characterization of the multilayer system, and intentional contamination for demonstration of the gettering properties.

Evaluation of Interface Trap Density in Advanced SOI MOSFETs

The density of traps at the top interface is difficult to assess in advanced SOI MOSFETs with high-K dielectric and ultrathin film. Searching for a characterization strategy, we compare various approaches: front-channel subthreshold slope, back-channel slope, and coupling coefficient between the front and back channels. The back-channel slope shows the largest variation with the front trap density. However, the resolution may not be sufficient for MOSFETs with very thin buried oxide.

Performance of SOI MOSFETs with Ultra-Thin Body and Buried-Oxide

The electrical characteristics in ultra-thin (8 nm) SOI-MOSFETs with 10 nm buried oxide thickness were studied. Threshold voltage was effectively controlled for both of N-channel and P-channel SOI-MOSFETs even in the short devices (45 nm). No degradation of the mobility due to the use of thin buried oxide could be detected. Through appropriate back-gate biasing, the performance of ultra-thin SOI-MOSFETs can be improved dramatically. In P-channel SOI-MOSFETs, the hole mobility measured in volume conduction regime is higher than when only one interface (Si/high-K or Si/SiO2) is activated. This gain makes the hole mobility comparable with the universal mobility law and is promising for performance enhancement in CMOS circuits.

Experimental investigation of ESD design window for fully depleted SOI N-MOSFETs

In this article, the impact in FDSOI technology, of ground plane and buried oxide (BOX) size on the robustness and on the NMOS triggering voltage (Vt1) is shown. We show experimentally that firstly thin BOX devices are more robust than thick BOX devices and secondly with a higher Vt1, thin BOX device purposes a larger range to trigger ESD network and to optimize design.

Numerical analysis of the self-heating effect in SGOI with a double step buried oxide

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator (SGOI) n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs), this paper proposes a novel device called double step buried oxide (BOX) SGOI, investigates its electrical and thermal characteristics, and analyzes the effect of self-heating on its electrical parameters. During the simulation of the device, a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered. A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed. By reducing moderately the BOX thickness under the channel, the channel temperature caused by the self-heating effect can be effectively reduced. Moreover, mobility degradation, off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed. Therefore, SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.