Abstract
With the current scenario of different candidates to lead the road to 14nm node and beyond, this work presents a thorough Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the scaling possibilities of Extremely Thin Silicon on Insulator technology (ETSOI) considering the impact of Buried Oxide (BOX) engineering on the electrostatic integrity of devices addressed for the forthcoming technological nodes. The simulations show that the combined use of Ultra Thin BOX (UTBOX) and Ground Plane/Back Bias (GP/BB) plane are enabling techniques to ensure an adequate control of Short Channel Effects (SCEs) in order to extend the roadmap of ETSOI technology down to 11nm node and beyond. BOX engineering also makes possible a redefinition of standard scaling rules relaxing the constraints on LG/TSi ratio with the advantage over Multiple Gate FETs (MuGFETs) based architectures of a fully compatible fabrication process with main stream planar technologies.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
