SOI high‐voltage LDMOS with novel triple‐layer top silicon based on thin BOX

Abstract

A novel SOI high-voltage LDMOS with a triple-layer top silicon (TLTS) is investigated. The top silicon layer of the TLTS LDMOS consists of n− silicon with a p-top layer, p− silicon in the middle, and n+ silicon on the interface. On the condition of high-voltage blocking state, the electric fields of the drift region and BOX are modulated and optimised by the triple-layer top silicon, respectively, which induces a high BV of 624 V for the TLTS LDMOS with a thin buried oxide layer (BOX) of 0.4 µm. Compared with several SOI devices, the proposed TLTS LDMOS has a higher figure-of-merit.