Thermal Vias Research Articles

Thermal Solution Maps: A Strategy for Thermal Design of Three-Dimensional Packages

Three-dimensional (3D) packages are of considerable interest at the present time as a means for heterogeneous high-performance integration of disparate digital, analog, optical, and MEMS technologies. However, their design is challenged by several issues, including the appropriate choice of thermal solution to be used in the 3D stack. Suboptimal placement of heat sources/sinks leads to hot spots, which are detrimental to package reliability. The broad goals of this study are to determine the appropriate cost and reliability-constrained heat-sinking solutions through an optimal placement of spatially distributed energy transporting elements. The heat-sinking solutions considered in this study include microchannels, and thermal vias. We conduct a microchannel analysis to develop a reduced model of the heat and mass transfer characteristics of the microchannel. We also develop optimization techniques and tools for thermal solution design of three-dimensional packages. We use a nonuniform “real-life” microprocessor power map for the illustration of the procedure. We subsequently obtain the optimal size and location of the thermal vias and microchannels in a 3D stack by minimizing a proposed multi-objective criteria. Finally, we develop and illustrate the notion of design maps that would guide the designers in the selection of appropriate thermal solution technologies for 3D packages.

Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power

The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126 times faster to obtain temperature, and reduces the number of thermal vias by 2.04 times under the same temperature bound.

Theoretical and experimental characterization of heat dissipation in a board-level microelectronic component

In this study, the steady-state heat transfer characteristics of a board-level microelectronic component in natural convection are investigated through numerical modeling and experimental validation. A typical plastic ball grid array (PBGA) package assembled to a piece of printed circuit board (PCB) is considered as the test vehicle. To achieve the goal, a three-dimensional (3D) finite element (FE) modeling technique that utilizes an effective heat conduction FE model together with empirical heat transfer (HT) coefficient correlation models for describing surface heat transfer of the electronic assemblies is applied for theoretical characterization while an infrared thermography-based technique (IRT) that incorporates FE modeling and IR thermography measurement, and a thermal test die measurement (TTDM) technique are applied for experimental validation. To facilitate the IR thermography measurement, the black paint coating technique is applied. The emissivity and optimal thickness of the specific black paint are explored through simple experiments. Besides, the uncertainty in the TTDM for the chip junction temperature measurement is also assessed. By the validated theoretical analysis model, numerical investigation of heat transfer enhancements, such as thermal balls and thermal vias, in the board-level microelectronic component is also accomplished, and eventually, an extensive thermal design guideline is accordingly provided.

Thermal analysis of high power GaN-based LEDs with ceramic package

In this paper we present thermal analysis of three kinds of ceramic package designs for high power LEDs. The analysis was made by transient thermal measurement and thermal simulation using the Finite Volume Method. The three ceramic packages under investigation employ same configuration of GaN-based chip, but they have different size and distribution of thermal vias. Three designs of LED packages resulted in significantly different thermal behaviors. Thermal behaviors, described as thermal resistance, of the three packaging designs were compared and evaluated as functions of bulk thermal resistance, spreading resistance, and surface roughness. The deviation between the simulated results and measured data were attributed to the different surface roughness in the interfaces between the packaging components. It was demonstrated that the junction temperature decreases with the effective contact area ratio in the LED packages.

Nanoscale Thermal Transport and Microrefrigerators on a Chip

In this paper we review recent advances in nanoscale thermal and thermoelectric transport with an emphasis on the impact on integrated circuit (IC) thermal management. We will first review thermal conductivity of low-dimensional solids. Experimental results have shown that phonon surface and interface scattering can lower thermal conductivity of silicon thin films and nanowires in the sub-100-nm range by a factor of two to five. Carbon nanotubes are promising candidates as thermal vias and thermal interface materials due to their inherently high thermal conductivities of thousands of W/mK and high mechanical strength. We then concentrate on the fundamental interaction between heat and electricity, i.e., thermoelectric effects, and how nanostructures are used to modify this interaction. We will review recent experimental and theoretical results on superlattice and quantum dot thermoelectrics as well as solid-state thermionic thin-film devices with embedded metallic nanoparticles. Heat and current spreading in the three-dimensional electrode configuration, allow removal of high-power hot spots in IC chips. Several III-V and silicon heterostructure integrated thermionic (HIT) microcoolers have been fabricated and characterized. They have achieved cooling up to 7 degC at 100 degC ambient temperature with devices on the order of 50 mum in diameter. The cooling power density was also characterized using integrated thin-film heaters; values ranging from 100 to 680 W/cm2 were measured. Response time on the order of 20-40 ms has been demonstrated. Calculations show that with an improvement in material properties, hot spots tens of micrometers in diameter with heat fluxes in excess of 1000 W/cm2 could be cooled down by 20 degC-30 degC. Finally we will review some of the more exotic techniques such as thermotunneling and analyze their potential application to chip cooling

Placement of thermal vias in 3-D ICs using various thermal objectives

As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3-D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional two-dimensional integrated circuits (2-D ICs). In this paper, thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities. The method, which uses finite-element analysis (FEA) to calculate temperatures quickly during each iteration, makes iterative adjustments to these thermal conductivities in order to achieve a desired thermal objective and is general enough to handle a number of different thermal objectives such as achieving a desired maximum operating temperature. With this method, 49% fewer thermal vias are needed to obtain a 47% reduction in the maximum temperatures, and 57% fewer thermal vias are needed to obtain a 68% reduction in the maximum thermal gradients than would be needed using a uniform distribution of thermal vias to obtain these same thermal improvements. Similar results were seen for other thermal objectives, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.

Thermal analysis and optimization for a ball grid array package

In this study, a computational fluid dynamics (CFD) approach is employed for heat transfer analysis of a ball grid array (BGA) package that is widely used in the modern electronics industry. Owing to the complicated geometric configuration of the BGA package, the submodel approach is used to investigate in detail the temperature distributions of thermal vias and solder balls. The effective thermal resistance of a BGA package has been successfully obtained from numerical simulations. An artificial neural network (ANN) is trained to establish the relationship between the geometry input and the thermal resistance output. The well-trained network is then coupled with the complex optimization method to search for the optimum design of the BGA package to achieve the lowest thermal resistance. The results of this study provide the electronic packaging industry with a reliable and rapid method for heat dissipation design of BGA packages.

Thermal Performance Optimization of Radio Frequency Packages for Wireless Communication

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A three-dimensional conjugate numerical study was conducted to evaluate the thermal performance of gallium arsenic die packaged in quad flat no-lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: (1) one for standard operating parameters and (2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5 °C (or 119 °C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186 °C (or 125 °C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126 °C (66 °C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe, and additional board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy versus solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an infrared microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Board Via Effect On Thermal Performance Of A Leadless Package

The thermal resistance “junction-to-ambient” θJA of a leadless plastic package P-VQFN-24 on a 4-layer (2s2p) PCB according to standard JESD51-7 was calculated using the FE code ANSYS® and measured using samples with thermal test dies. Measurements were done for chip sizes of 1.6mm2 and 3.2mm2, calculations for several die sizes to cover the possible range of this package from 0.5–4.2mm2. Package mounting on two different PCB types was investigated: one has an insulating solder resist layer in the area below the exposed die pad of the package, the other has Cu-lands for die pad soldering and 4 thermal vias for heat conduction to a buried Cu-ground layer. With this mounting condition, θJA can be reduced from 88 to 46 K/W and from 80 to 43 K/W for the small and the larger die, respectively. However with the die pad soldered to the PCB also 3 of 14 samples showed a θJA of about 60K/W in measurements. If these samples where omitted, measurement and simulation agreed within 6% or better. To clarify the cause of the bad thermal performance of some samples, an analysis using Acoustic Scanning Microscopy (SAM), X-ray photography and finally cross-sectioning was done. Die attach and solder quality was found to be good. The reason for bad thermal performance was the thermal via quality. The metal wall thickness in a via hole always steadily decreased with depth, in some vias of bad samples even to zero before contacting the buried ground plane. In that case a thermal via has no effect any more. Besides presenting thermal data of the VQFN-24 package, the work also shows the strong influence of PCB mounting details on the thermal performance of packages with exposed die pad.

Micro heat pipes in low temperature cofire ceramic (LTCC) substrates

With projected power densities above 100 W/cm/sup 2/ for devices, new methods for thermal management from the heat generation at the die to heat removal to the ambient must be addressed. By integrating micro heat pipes directly within the ceramic substrate, effective thermal conductivity for spreading heat in both radial and axial directions was achieved. New materials and processes were developed to fabricate the unique components required to handle high thermal loads. Enhanced thermal vias to minimize the thermal impedance through the ceramic in the evaporator and condenser sections were developed, increasing the effective thermal conductivity from 2.63 to near 250 W/m-/spl deg/C. The use of an organic insert fabricated into the desired complex shape using rapid prototyping methods, coupled with the viscoelastic flow of the low temperature cofire ceramic (LTCC) during lamination, allowed complex shapes to be developed while ensuring uniform green tape density during lamination prior to tape firing. Large cavities, three-dimensional fine structures and porous wicks for capillary 3-D flow have been utilized to fabricate the heat pipes. Heat pipes and spreaders, utilizing water as the working fluid, have been demonstrated operating with power densities in excess of 300 W/cm/sup 2/.

Novel materials for thermal via incorporation into SOI structures

Self-heating effects in ICs on silicon-on-insulator (SOI) substrates are due to the thick buried oxide layer present in the SOI substrate. Silicon dioxide has a poor thermal conductivity value (0.4-1.2WK-1m-1), compared with silicon (150WK-1m-1). In order to minimize this self-heating, the use of multiple-layer structures as thermal vias (TV) is investigated. The vias have been fabricated as sandwich layers with thin SiO2 (20 nm) enclosing low pressure chemical vapor deposited (LPCVD) silicon layers (1 βm), all IC compatible materials. The LPCVD silicon layers consisted of either polycrystalline silicon or a combination of amorphous silicon and polysilicon. Electrical testing of the oxide/silicon structures has shown that inclusion of an amorphous silicon layer in the oxide sandwich improves the interface between the oxide and the silicon layer. This provides better electrical stability with an operational capability >30 V. The capacitance of the multi-layer structure (96 pF), as measured at frequencies ≥1 MHz, confirms that the polysilicon behaves as a dielectric layer at these frequencies. Thermal conductivity assessment, using a four-terminal resistor structure, shows that the multilayer via offers an improved thermal conductivity (3.5WK-1m-10 when compared to a 1-βm homogenous buried oxide layer (0.8WK-1m-1)

An investigation of thermal enhancement on flip chip plastic BGA packages using CFD tool

This paper demonstrates the advantage of applying Predictive Engineering in the thermal assessment of a 279 inputs/outputs (I/Os), six-layer, depopulated array flip chip PBGA package. Thermal simulation was conducted using a computational fluid dynamics (CFD) tool to analyze the heat transfer and fluid flow in a free convection environment. This study first describes the modeling techniques on a multilayer substrate, thermal vias, solder bumps, and printed circuit board (PCB). For a flip chip package without any thermal enhancement, more than 90% of the total power was conducted from the front surface of the die through the solder ball interconnects to the substrate, then to the board. To enhance the thermal performance of the package, the heat transfer area from the backside of the die needs to increase dramatically. Several thermal enhancing techniques were examined. These methods included a copper heat spreader with various thicknesses and with thermal pads, metallic lid, overmolded with and without a heat spreader, and with heat sink. An aluminum lid and a heat sink gave the best improvement; followed by a heat spreader with thermal pads. Both methods reduced thermal resistance by an average of 50%. Detailed analyses on heat flow projections are discussed.

STEADY STATE AND TRANSIENT THERMAL ANALYSIS OF CHIP SCALE PACKAGES

This paper summarizes a study of chip scale packages (CSP) to determine their maximum allowable power dissipation within typical system level environments. These results can be used to determine the applicability of utilizing CSPs from the standpoint of die power dissipation. Both steady state and transient thermal performance is covered in this study. The steady state portion used in-house software, while closed-form solutions were utilized for the transient analysis. The steady state power limit, while governed by a number of parameters, is dependent mainly upon system level parameters (heatsinking, cooling mode — i.e., natural or forced convection, and PCB power loading). Thermal enhancement features (e.g. thermal vias and bumps) are not generally effective in increasing the maximum power that can be dissipated by the package in the end use environment. The variables investigated in the steady state study included die size, thermal vias and bumps, the addition of a heatsink, natural/forced convection boundary conditions, printed circuit board (PCB) heat loading, and PCB thermal conductivity. The transient portion considered die size, pulse shape and duration, and the addition of a heatsink. For relatively short duration transients (e.g. switching an inductive load), the power limit is governed by the die geometry; magnitude, shape and duration of the heating pulse; and the starting and maximum allowable temperatures of the junction.

Optimization for thermal and electrical wiring for a flip-chip package using physical-neural network modeling

It is shown in this paper that artificial neural networks (ANNs) offer an attractive approach to finding a global optimum for both thermal and electrical wiring performance in electronic packages. The variables used for the optimization are internal thermal resistance, and electrical wiring both of which are expressed as functions of size and number of vias. First, the thermal calculations are performed by solving the steady heat conduction equation in a three-dimensional (3-D) domain. The temperature profiles and chip-to-case thermal resistances are obtained for different number and sizes of thermal vias. This thermal data set is used to "train" an ANN model. Our "simple to complex" and simultaneous testing and training procedure is used to develop an appropriate network with best predictive capabilities. Then, an algebraic expression for the electrical wiring density on the chip is derived as a function of the via number and size for a simple wiring layout. Using this expression along with the ANN model for the thermal resistance, we illustrate an efficient optimization method. The approach is general and is easily extendible to other more complex situations.

A>400 GHz f/sub max/ transferred-substrate heterojunction bipolar transistor IC technology

We report transferred-substrate AlInAs/GaInAs bipolar transistors. A device having a 0.6 μm×25 μm emitter and a 0.8 μm×29 μm collector exhibited f/sub /spl tau//=134 GHz and f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> >400 GHz. A device with a 0.6 μm×25 μm emitter and a 1.8 μm×29 μm collector exhibited 400 GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> 164 GHz f/sub /spl tau//. The improvement in f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> over previous transferred-substrate HBT's is due to improved base Ohmic contacts, narrower emitter-base and collector-base junction areas, and slightly reduced transit times. The transferred-substrate fabrication process provides electroplated gold thermal vias for transistor heat-sinking and a microstrip wiring environment on a low dielectric constant polymer substrate.

Laser-diode array packaging in opto-electronic multichip modules

An opto electronic multichip module (OE-MCM) constructed from optical polyimide waveguides on an OE substrate has been developed for high-speed, wideband communication systems. This paper describes the packaging of the laser-diode (LD) array on the OE substrate, which is composed of low-loss (0.4 dB/cm at 1.3 /spl mu/m) optical polyimide waveguides on a copper-polyimide multilayer substrate. High-speed (Gbit/s) electrical signals are transmitted through electrical lines in the copper-polyimide layers. A junction-up, five-channel InGaAsP edge-emitting LD array is aligned to the waveguides in the plane direction with an error margin of 2 /spl mu/m by using a standard surface for vertical positioning. The bottom of the LD array is connected to columnar thermal vias under the bonding area for heat dissipation. The emitted light power is considered to be stable because no kinks and good linearity are observed in the I-L characteristics of the coupled LD array. The coupling loss was estimated to be 6.5 dB with a deviation between channels of /spl plusmn/0.3 dB.

Thermal characterization of a Tape Carrier Package

The unenhanced thermal performance of 20 mm Tape Carrier Packages (TCP) packages on 8 layer boards with internal planes is 19/spl deg/C/W. Package thermal resistance /spl Theta//sub jc/ has been measured at 2/spl deg/C/W. Simple PCB enhancements such as the addition of thermal vias, alone or with the use of low profile heat sinks, brings the thermal performance in line with requirements for mobile computing platforms which do not have forced convection cooling options available. With forced convection cooling, devices with power dissipation requirement of 5/spl deg/C/W and higher can be packaged in TCP format.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Heat Conduction in Concentric Cylinders: An Application to Electronic Packages

A numerical analysis on the heat conduction characteristics of concentric cylinders is presented. The study is relevant to heat transfer in electronic equipment wherein cylindrical electrical conductors or thermal vias (typically characterized by high thermal conductivities) are surrounded by electrical insulators having a different thermal conductivity. The heat conduction equation is solved using a control-volume finite-difference technique. Results are presented in terms of the thermal spreading resistance, the heat removal contribution of the inner cylinder (pin) and the heat spreading contribution of the surrounding material for a wide range of governing parameters. In particular, the effects of the thermal conductivities of the cylinders and the geometric dimensions on the heat spreading characteristics are investigated. It is shown that there is no spreading when the ratio of the conductivity of the pin to the conductivity of the surrounding material (k/K) is larger than about 1000; as found in copper pins surrounded by Teflon or Fr-4 type of a dielectric material. Substantial reduction in the overall thermal resistance is obtained with k/K less than 10, which could be practically achieved by using silicon carbide or aluminum nitride as the surrounding material.

Thermal design for high-speed high-density multichip module

The boundary conditions of models for finite element analysis of the thermal design of high-speed high-density multichip modules are examined, principally the thermal via and heat sink, and a model that improves the accuracy of heat transfer analysis simulation is investigated. It is found that in evaluating the effectiveness of thermal vias in heat loss, simulation can be made to yield results close to observed values by considering the substrate a compound material with a uniform thermal conductivity coefficient determined by the ratio of thermal via cross section area to substrate area. A thermal via area ratio of 10% is satisfactory both from the standpoint of manufacturing and for effectiveness in decreasing thermal resistance. Also, in the present model the heat transfer coefficient of the heat sink can be determined by using air speeds and comparison with observed results. It is concluded that the model is capable of highly accurate simulation of thermal via and heat sink conditions and can be effective in the thermal design of high-speed, high-density multichip modules.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low temperature co-fired glass ceramic high density interconnect substrate with improved thermal management

A hybrid integrated regulator/modulator with a digital and analog signal bus system for power conditioning of a transmit/receive module having a density figure of merit of 69 W/in/sup 3/ and 845 W/lb is described. High-density multichip power conditioning modules were designed using a low-temperature cofired ceramic as the base substrate. The design was fabricated, tested, and delivered. Design considerations, guidelines, and fabrication concerns are discussed. Aspects discussed include high-density computer aided design and packaging concepts, the regulator/modulator approach to power conditioning, design guidelines and substrate characteristics of the glass-ceramic material system, thermal management solutions for high-powered chips, and reliability and performance data on the finished substrate and module. Emphasis is on the improved processing of blind thermal slots and cofired top metallization. An appreciable improvement of thermal conductivity with thermal vias was achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>