Board Via Effect On Thermal Performance Of A Leadless Package

Abstract

The thermal resistance “junction-to-ambient” θJA of a leadless plastic package P-VQFN-24 on a 4-layer (2s2p) PCB according to standard JESD51-7 was calculated using the FE code ANSYS® and measured using samples with thermal test dies. Measurements were done for chip sizes of 1.6mm2 and 3.2mm2, calculations for several die sizes to cover the possible range of this package from 0.5–4.2mm2. Package mounting on two different PCB types was investigated: one has an insulating solder resist layer in the area below the exposed die pad of the package, the other has Cu-lands for die pad soldering and 4 thermal vias for heat conduction to a buried Cu-ground layer. With this mounting condition, θJA can be reduced from 88 to 46 K/W and from 80 to 43 K/W for the small and the larger die, respectively. However with the die pad soldered to the PCB also 3 of 14 samples showed a θJA of about 60K/W in measurements. If these samples where omitted, measurement and simulation agreed within 6% or better. To clarify the cause of the bad thermal performance of some samples, an analysis using Acoustic Scanning Microscopy (SAM), X-ray photography and finally cross-sectioning was done. Die attach and solder quality was found to be good. The reason for bad thermal performance was the thermal via quality. The metal wall thickness in a via hole always steadily decreased with depth, in some vias of bad samples even to zero before contacting the buried ground plane. In that case a thermal via has no effect any more. Besides presenting thermal data of the VQFN-24 package, the work also shows the strong influence of PCB mounting details on the thermal performance of packages with exposed die pad.