Abstract

Package substrate physical design effects thermal conduction in the substrate and, hence, the thermal performance of the package. Package physical design involves geometric, material, and feature layout parameters. Effect of these physical design parameters on the thermal performance (characterized by junction to ambient thermal resistance, /spl Theta//sub ja/, junction-to-board thermal resistance /spl Psi//sub jb/, and junction to case thermal resistance /spl Psi//sub jT/) of flip-chip plastic ball grid array (FC-PBGA) has been studied using experimentally validated conjugate heat transfer models. Package level thermal performance of flip-chip plastic ball grid array (FC-PBGA) packages has been predicted using experimentally validated mechanistic methodologies. The resulting conjugate heat transfer models have been solved using methods of computational fluid dynamics (CFD) under natural and forced convection for freestream velocities upto 2 m/s. The following ranges of parameters have been investigated: substrate size of 25 mm, die sizes of 6.19/spl times/7.81 mm and 9.13/spl times/12.95 mm, substrate (via density) thermal conductivities: no vias to 5 W/(m K), C4 pitch: 250 /spl mu/m, natural and forced convection flows, the later with freestream velocities 0.5 to 2 m/s. Based on this study the following conclusions have been drawn: 1. It is concluded that thermal vias (and hence the thermal conductivity of the substrate under the die) have significantly higher impact on package thermal performance than the substrate vias outside the die foot print. 2. By strategically placing sufficiently number of vias in the substrate, the thermal resistance of the package can be decreased by 35-40% thereby pushing the limits of power dissipation under constrained conditions. 3. It is noted that increasing the number of visa under the die that results in thermal conductivity above 2 W/(m K), the thermal performance of the packages improve very little showing diminishing returns.

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