TFT Devices Research Articles

P‐27: A Novel PWM Driving Pixel Circuit with Metal‐Oxide TFTs for MicroLED Displays

A pixel circuit for micro‐LED display has been developed with IGZO TFT device. By using pulse width modulation method, the pixel circuit can operate at high peak current and low duty ratio to keep micro‐LED at high emission efficiency and stable color performance.

Improvement of Strained Negative Bias Temperature Instability in Flexible LTPS TFTs by a Stress-Release Design

In this study, the negative bias temperature instability (NBTI) under mechanical strain conditions of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a stress-release structure was investigated. With both electrical and mechanical stresses simultaneously applied, more significant degradation behaviors will be observed in standard TFT devices because mechanical stress makes it easier to generate strain in Si–H bonds, thus benefiting the process of electrochemical reaction. By employing a stress-release shape in the poly channel, mechanical stress, which mainly accumulates at the width edge of the poly-Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, is moved away from the main channel; thus, fewer strained Si–H bonds can participate in the electrochemical reaction compared to the standard structure. Therefore, the degradation of devices under strained NBTI is effectively mitigated, such that the reliability of the devices is enhanced. These observations were obtained using electrical characteristics and extraction of the trap state distribution.

From stretchable and healable to self-healing semiconducting polymers: design and their TFT devices

This review concisely elaborates the advancement from stretchable toward autonomous self-healable semiconducting polymers owing to their long-term use and enhanced reliability, maintenance, and durability for modern thin-film transistor devices.

Positive-Feedback-Based Design Technique for Inherently Stable Active Load Toward High-Gain Amplifiers With Unipolar a-IGZO TFT Devices

This letter presents analysis of an inherently stable positive-feedback-based active load, first reported in our prior work, to realize high gain analog amplifiers using unipolar a-IGZO TFT technology. Additionally reported are theoretical performance bounds and design guidelines to maximally utilize a general positive-feedback scheme for the active load while maintaining stability. To demonstrate a design implementation, a single stage fully differential operational transconductance amplifier with common mode feedback has been manufactured and measured to have 40-dB open-loop gain at dc and a unity gain frequency of 61 kHz while driving a 30-pF load capacitance.

Improving Device Characteristics of Dual-Gate IGZO Thin-Film Transistors with Ar-O2 Mixed Plasma Treatment and Rapid Thermal Annealing.

In this study, high-performance indium–gallium–zinc oxide thin-film transistors (IGZO TFTs) with a dual-gate (DG) structure were manufactured using plasma treatment and rapid thermal annealing (RTA). Atomic force microscopy measurements showed that the surface roughness decreased upon increasing the O2 ratio from 16% to 33% in the argon–oxygen plasma treatment mixture. Hall measurement results showed that both the thin-film resistivity and carrier Hall mobility of the Ar–O2 plasma–treated IGZO thin films increased with the reduction of the carrier concentration caused by the decrease in the oxygen vacancy density; this was also verified using X-ray photoelectron spectroscopy measurements. IGZO thin films treated with Ar–O2 plasma were used as channel layers for fabricating DG TFT devices. These DG IGZO TFT devices were subjected to RTA at 100 °C–300 °C for improving the device characteristics; the field-effect mobility, subthreshold swing, and ION/IOFF current ratio of the 33% O2 plasma–treated DG TFT devices improved to 58.8 cm2/V·s, 0.12 V/decade, and 5.46 × 108, respectively. Long-term device stability reliability tests of the DG IGZO TFTs revealed that the threshold voltage was highly stable.

Effect of HfO2-Based Multi-Dielectrics on Electrical Properties of Amorphous In-Ga-Zn-O Thin Film Transistors

We report the fabrication of bottom gate a-IGZO TFTs based on HfO2 stacked dielectrics with decent electrical characteristics and bias stability. The microscopic, electrical, and optical properties of room temperature deposited a-IGZO film with varied oxygen content were explored. In order to suppress the bulk defects in the HfO2 thin film and hence maximize the quality, surface modification of the SiNx film was investigated so as to achieve a more uniform layer. The root mean square (RMS) roughness of SiNx/HfO2/SiNx (SHS) stacked dielectrics was only 0.66 nm, which was reduced by 35% compared with HfO2 single film (1.04 nm). The basic electrical characteristics of SHS-based a-IGZO TFT were as follows: Vth is 2.4 V, μsat is 21.1 cm2 V−1 s−1, Ion/Ioff of 3.3 × 107, Ioff is 10−11 A, and SS is 0.22 V/dec. Zr-doped HfO2 could form a more stable surface, which will decrease the bulk defect states so that the stability of device can be improved. It was found that the electrical characteristics were improved after Zr doping, with a Vth of 1.4 V, Ion/Ioff of 108, μsat of 19.5 cm2 V−1 s−1, Ioff of 10−12 A, SS of 0.18 V/dec. After positive gate bias stress of 104 s, the ΔVth was decreased from 0.43 V (without Zr doping) to 0.09 V (with Zr doping), the ΔSS was decreased from 0.19 V/dec to 0.057 V/dec, respectively, which shows a meaningful impact to realize the long-term working stability of TFT devices.

Study of InGaZnO Thin Film Transistors With Dual Treatment of Pre-Oxidation ZrO2 High-κ Dielectric and Post-Oxidation InGaZnO Channel by Neutral Beam System

With better field-effect mobility (&gt;10 cm2/V·S), smaller subthreshold swing (S.S), and other electrical characteristics, amorphous IGZO thin film transistors (a-IGZO TFTs) has been studied extensively for its promising applications, such as liquid crystal displays and flat-panel displays. In this investigation, TFT devices are experimented to enhance the electrical characteristics. Atmosphere Pressure-PECVD (AP-PECVD) is used to deposit a-IGZO, which is designed as device channel layer. In order to maintain enough gate control ability with thinner effective oxide thickness (EOT), high-κ material ZrO2 is used as dielectric, lowering the gate leaking current. With post dual neutral beams O2 plasma treated on both a-IGZO channel layer 400 W and ZrO2 dielectric 100 W, the best result for experimental devices show that the a-IGZO TFT has electrical characteristics of field-effect mobility of 22.22 cm2/V·S, threshold voltage (VT) of 2.86 V, S.S of 74 mV/decade, and Ion/Ioff ratio of 8.2×105. Keywor

Recent progress of oxide-TFT-based inverter technology

Oxide semiconductor-based thin-film transistor (oxide-TFT) technology have gained significant attention since the innovation of n-channel oxide-TFT using ZnO and amorphous In–Ga–Zn–O (a-IGZO) channels because of their superior device properties including excellent electrical property such as high TFT mobility over >10 cm2/Vs and the low-cost manufacturability originating from the low-temperature processability. Already, n-channel a-IGZO-TFT is widely employed as a TFT pixel switching backplane for several high-performance active-matrix flat-panel displays, and oxide-TFT technology to date is well acknowledged as the best TFT technology for future device applications in the wide range area of electronics such as sensors, Internet of things (IoT), energy-harvesting, medical/bio-interface device, etc. Therefore, the development of large-scale circuit beyond discrete TFT device level becomes increasingly important and is vital to advance the next stage of oxide-TFT technology. In particular, developing oxide-TFT-based inverter device technology is the key for developing several digital and analog circuits. In this paper, the recent progress and challenges in oxide-TFT-based inverter technology, including unipolar NMOS, PMOS, CMOS, and CMOS-like inverters using ambipolar oxide-TFT, are reviewed.

Investigation of degradation mechanisms in small scaled amorphous-indium-gallium-zinc-oxide thin-film-transistors

We measured the stability of small-sized trench devices with different specifications under negative bias. The degradation behavior of the electrical characteristics of the device caused by the channel size was analyzed. It was found that the passivation caused by the increase of the channel width was not completely generated by charge trapping in the passivation layer and the interface between the passivation layer and the active layer. The parasitic effect related to the channel length and the drain-induced barrier lowering effect together affect the electrical stability of the device. This shows that with the development of small-sized TFT devices, the influence of size on the device begins to appear. As such the size factor must be considered when designing the device. For the instability caused by these devices themselves, post-processing can be used to improve the stability.

A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

P‐13.8: Evaluation of the Structure‐Capacitance Relationship in OLED Device and the Influence of Capacitance Variation on Pixel Circuit

Over the past years, active‐matrix organic light‐emitting diode (AMOLED) has established a commanding position in displays for smart phones, smart watches and TVs. However, AMOLED display still faces challenges in pursuing high‐level performance as TFT and/or OLED suffer device‐level variation and dynamic shifting resulting from the aging effect. Thus, a variety of internal compensation circuits, which are designed to partially compensate these harmful variation and dynamic shifting, have been implemented into pixel circuits of AMOLED products. Previous studies have mainly focused on the instability of TFT device, however the capacitance of OLED device could also affect the overall compensation effect. In this study, the structure‐capacitance relationship of OLED device is systematically presented and the influence of capacitance variation on the pixel circuits at compensation stage is also discussed.

Mobility improvement of LTPS thin film transistor using stacked capping layer

Low-temperature polycrystalline Si (LTPS) has been widely used to achieve large-area and high-speed TFT devices. In this regard, the enhancement in the mobility and stability of LTPS TFTs was investigated with the insertion of amorphous silicon (a-Si:H) capping layers at the insulator/poly-Si junction. Prior to capping layer deposition, the polycrystalline Si active region was plasma pre-treated under N2O or NH3/N2O ambience to refine the device characteristics. A high field effect mobility (μFE) of 90 cm2/Vs with a subthreshold swing (SS) of 1.21 V/dec was obtained from N2O treated non-capped LTPS TFT. The inclusion of a-Si:H(n)/a-Si:H(i) stacked capping layer at the gate insulator/poly-Si junction enhanced μFE to 152 cm2/Vs and decreased the SS to 0.69 V/dec. In contrast, the single capping layer of a-Si:H(i) and a-Si:H(n) showed feeble μFE improvements. The mechanism behind the μFE increase for the a-Si:H(n)/a-Si:H(i) stacked capping layer was explained using the atlas TCAD simulator. The grain boundary trap (Ntrap) density also decreased drastically with the insertion of the capping layer. A low and stable Ntrap value of 3.8 × 1011 cm−3 was obtained for a-Si:H(n)/a-Si:H(i) stacked capping layer with N2O pre-treatment, which may play a major role in enhancing the mobility and can be implemented for next-generation LTPS TFTs.

P‐7: In‐Cell‐Touch Display Design Using Gate Driver Circuits Integrated within Active Area and De‐Mux Source Driver

In this article, we develop a new In‐cell touch TFT LCD display with gate driver circuits integrated within the active area and De‐mux driver. We designed a GOA driver circuit based on LTPS technology, which integrated GOA circuit into AA and realized In‐cell touch technology. Due to the LTPS technology, the GOA TFT device and wiring are integrated within pixels, and the loss of aperture rate is reduced. However, as the GOA circuit is integrated inside Pixel and simultaneously the panel uses De‐mux source driver and In‐cell touch driver, the display data is vulnerable to GOA signal interference. We solved the influence of GOA on display through the new pixel design and De‐mux driver. Finally, we made the 6.53″ De‐mux 1 to 3 In‐cell touch LCD display and got a good display effect.

P‐1.11: Performance Improvement of a‐IGZO Thin‐Film Transistor By Using Ta2O5/SiO2 Double‐layer Gate Dielectric

a‐IGZO TFT devices are receiving great attention, not only the new display applications require higher mobility, but still need to overcome shortcomings such as high threshold voltage and high sub‐threshold swing. In this work, a double‐layer gate dielectric (Ta2O5/SiO2) a‐IGZO TFT device is proposed and compared with a single‐layer gate dielectric (SiO2) device. The results appeal that the mobility is effectively improved, the sub‐threshold swing is reduced, the On‐Off current ratio is increased, and the operating voltage is small. Comparisons of single‐layer and double‐layer gate dielectric structures are discussed through energy bandgap analysis. COMSOL simulations and analysis of the electric field and potential distributions of the devices are carried out to explain the reason for the performance improvement in principle.

27.2: Invited Paper: Towards High Performance Gate Electrodes: Resistance Reduction in Molybdenum Films by Seed Layer Application

Molybdenum gate line resistance is a critical item for future high end TFT devices. While conventional Molybdenum lines are well established, the application of better conducting materials poses new challenges to stability and process integration. In our work we investigate and discuss application of different seed layer materials to lower the line resistance of Molybdenum while keeping its superior processability. Our results show that the application of a thin seed layer below the Molybdenum layer can reduce resistance of main Molybdenum film by up to 30%.

Printable Ultra‐Flexible Fluorinated Organic–Inorganic Nanohybrid Sol–Gel Derived Gate Dielectrics for Highly Stable Organic Thin‐Film Transistors and Other Practical Applications

AbstractA novel fluorinated organic–inorganic (O–I) hybrid sol—gel based material, named FAGPTi, is successfully synthesized and applied as a gate dielectric in flexible organic thin‐film transistors (OTFTs). The previously reported three‐arm‐shaped alkoxysilane‐functionalized amphiphilic polymer yields a stable O–I hybrid material consisting of uniformly dispersed nanoparticles in the sol‐state. Here, a fluorinated precursor is introduced into the system, making it possible to realize more stable spherical composites. This results in long‐term colloidal stability (≈1.5 years) because composite growth is strongly inhibited by the presence of fluorine groups with intrinsically strong repulsive forces. Additionally, the FAGPTi film is easily deposited via thermally annealed sol–gel reactions; the films can be successfully fabricated through the printing method, and exhibit excellent flexibility and enhanced insulating properties compared to existing materials. OTFTs with FAGPTi layers show highly stable driving characteristics under severe bending conditions (1.9% strain). Integrated logic devices are also successfully operated with these OTFTs. Additionally, it can facilely be applied to amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) TFT devices other than OTFT. Therefore, this synthetic strategy can provide useful insights into the production of functional O–I hybrid materials, enabling the efficient fabrication of electronic materials and devices exhibiting these properties.

Study on Properties of Cu Barrier Materials in TFT devices

Study on Properties of Cu Barrier Materials in TFT devices

Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions

This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS, a stress-induced hump current in subthreshold region is observed and is caused by the charge trapping into parasitic transistors along the channel width edges. This phenomenon is attributed to carrier injection occurring along the width edges since a high electric field is located at that region, where lots of defects are generated due to the definition of the active area during the etching process. In this study, we show that the degradation in electrical characteristics during the gate bias operation resulted from the edge effect can be eliminated when the TFT devices utilize the channel width extension in the active layer. Electrical measurements, numeral calculations, and a TCAD electrical simulation confirm that this geometry, which includes a channel extension along the width direction, can dramatically reduce the carrier injection at the edges even though high electric field is mainly located at the width edges during gate bias operation.

A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area.

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the Vth and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions. In this study, we proposed that a TFT device requires a wider BTBT region because this limited region worsens the variations in the electrical characteristics of the TFT device. Two additional methods were proposed, one using vertical BTBT over a wide area through an additional poly-Si layer deposition and one widening the BTBT area through tilting implantation without an additional deposition process. The simulation results show that the variation of Vth is reduced to 10% through the extension of the BTBT area.

17‐1:Invited Paper:An Overview of Solutions for Achieving HDR LCDs

This article introduces the solutions to improve LCD HDR performance. Backlight solutions including passive, active driving mini LED backlight and halo effects are studied. High cell transmittance and enhanced TFT device reliability for high brightness are discussed. Furthermore, the vivid image and high contrast can be kept in high ambient light by applying AUO A.R.T. technology.