Abstract
Low-temperature polycrystalline Si (LTPS) has been widely used to achieve large-area and high-speed TFT devices. In this regard, the enhancement in the mobility and stability of LTPS TFTs was investigated with the insertion of amorphous silicon (a-Si:H) capping layers at the insulator/poly-Si junction. Prior to capping layer deposition, the polycrystalline Si active region was plasma pre-treated under N2O or NH3/N2O ambience to refine the device characteristics. A high field effect mobility (μFE) of 90 cm2/Vs with a subthreshold swing (SS) of 1.21 V/dec was obtained from N2O treated non-capped LTPS TFT. The inclusion of a-Si:H(n)/a-Si:H(i) stacked capping layer at the gate insulator/poly-Si junction enhanced μFE to 152 cm2/Vs and decreased the SS to 0.69 V/dec. In contrast, the single capping layer of a-Si:H(i) and a-Si:H(n) showed feeble μFE improvements. The mechanism behind the μFE increase for the a-Si:H(n)/a-Si:H(i) stacked capping layer was explained using the atlas TCAD simulator. The grain boundary trap (Ntrap) density also decreased drastically with the insertion of the capping layer. A low and stable Ntrap value of 3.8 × 1011 cm−3 was obtained for a-Si:H(n)/a-Si:H(i) stacked capping layer with N2O pre-treatment, which may play a major role in enhancing the mobility and can be implemented for next-generation LTPS TFTs.
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