Test Pattern Generation Research Articles

An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns

As the number of transistors in the fabricated circuits becomes extremely larger, not only single stuck-at faults, but also multiple stuck-at faults (MSAFs) are likely to happen in the circuits, especially for the large-scale circuit. Multiple faults are difficult to be fully covered due to the exponentially enormous number of all possible faults. Although there are methods proposed to deal with the multiple faults, they fail to generate compact test patterns to detect all faults within an acceptable running time. In order to solve these problems, this article proposes an incremental automatic test pattern generation method to deal with MSAFs. Instead of traversing the entire ${n}$ multiple fault list, the proposed method only selects the faults undetected by the existing test patterns for ${n-1}$ faults, and then generates additional test patterns. Staring from a complete test set for single faults, the proposed ATPG method can be incrementally applied to handle all multiple faults. Moreover, since the number of undetected faults that are selected is extremely smaller comparing to the total number of the entire fault list, the proposed method can generate compact test patterns to cover all faults within an acceptable running time.

An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests

Nowadays, many Integrated Systems embed auxiliary on-chip instruments whose function is to perform test, debug, calibration, configuration, etc. The growing complexity and the increasing number of these instruments have led to new solutions for their access and control, such as the IEEE 1687 standard. The standard introduces an infrastructure composed of scan chains incorporating configurable elements for accessing the instruments in a flexible manner. Such an infrastructure is known as Reconfigurable Scan Network or RSN. Since permanent faults affecting the circuitry can cause malfunction, i.e., inappropriate behavior, detecting them is of utmost importance. This paper addresses the issue of generating effective sequences for testing the reconfigurable elements within RSNs using evolutionary computation. Test configurations are extracted with automatic test pattern generation (ATPG) and used to guide the evolution. Post-processing techniques are proposed to improve the evolutionary fittest solution. Results on a standard set of benchmark networks show up to 27% reduced test time with respect to test generation based on RSN exploration.

Fpga Implementation of Active Neighborhood Pattern Sensitive Fault Testing Using Tiling Method

Test structure for Active Neighborhood Pattern Sensitive Fault (ANPSF) in memories with high switching speed is modeled in this paper. Algorithm for ANPSF testing is developed using type-1 neighborhood approach. The type-1 neighborhood, also known as tiling method has one victim and four aggressor cells. It is used to identify the ANPSF effect on base cell by the switching of patterns in the corresponding deleted neighborhood cells. The required test pattern can be generated using a Binary counter, Hamiltonian or Gray pattern generator where the two successive values differ in only one binary digit. The BIST architecture allows to incorporate the hardware required by the user to select the victim and corresponding aggressor cells to test the complete memory. It helps in application of test pattern for the memory circuit under test on user’s choice. The main objective of this model is to develop the architecture for tiling methodology with test pattern generator to detect the transitions in aggressor cells with edge detection technique. The proposed work enables to verify the response of victim cell which may cause a change in value resulting in an active neighborhood pattern sensitive fault scenario. The complete ANPSF model architecture for memory testing is developed using Verilog hardware descriptive language. The process of simulation and synthesis report is validated using Xilinx 14.2 and implemented on Nexys 4 DDR Artix 7 FPGA board.

Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems

Taking advantage of multicore architectures can provide significant improvement for many design automation problems. However, the parallelization procedure introduces challenges, such as workload duplication, limited search space exploration, and race contention among different threads. In this article, we propose a parallel framework for automatic test pattern generation using shared memory multicore systems that support test generation (TG) for both single-detect and multiple-detect fault models. The framework follows a two-epoch approach, each focusing on a different category of faults, during which a test seed generation is followed by compatibility merging. Various optimization techniques are incorporated in each epoch, designed to achieve higher speedup for the overall TG procedure without impacting much the test set size. A cluster-based approach is also presented, extending the proposed framework to consider multiple-detect fault models without affecting its efficiency. The obtained experimental results demonstrate increased speedup rates compared with the state-of-the-art multicore-based tools while, at the same time, the test inflation problem is restrained. For the multiple-detect extension, these properties are maintained despite the increased workload and the additional constraint of retaining the number of detections for each fault while merging.

Test Generation for Flow-Based Microfluidic Biochips With General Architectures

Flow-based microfluidic biochips have become a promising platform for complex biochemical assays. As the integration of such chips is increasing, a flexible general reconfigurable platform, fully programmable valve array (FPVA), has emerged. Such a 2-D array comprises regularly arranged valves using which flow-networks with different geometry, size, and connectivity can be constructed dynamically. However, the test generation for such arrays becomes challenging due to the large number of potential flow-networks and transportation paths that can be configured on-chip. In this article, we propose a strategy to generate efficient test patterns for FPVAs based on the concepts of test paths and cuts. These patterns together can cover multiple faults in both flow and control layers. We also introduce the concept of test trees and multiple cuts for a test pattern to deal with faults in FPVAs with multiple ports. Moreover, the proposed method can be applied to generate test patterns for traditional flow-based biochips with predefined architectures. The simulation results demonstrate that defects in FPVAs can be detected reliably by a limited number of test patterns generated by the proposed method. For traditional biochips with predefined architectures, these patterns also exhibit an improved test efficiency.

Design and Implementation of Reliability Analysis Tool using Real Time Data

To estimate the reliability of software numerous statistical methods are in practice. To accomplish the software reliability prediction in more accurate way there is a huge demand for data sets. The data sets that can be acquired as a result of testing the software can be used for predicting the reliability. The research work focuses on creating a layer of software design and testing method namely web software testing. The main purpose is to collect the erroneous data from real time. The reliability of software can be measured in different aspects like traffic handling capability when there are a greater number of users, the security level for cracking the passwords and the possibility of different combinations of errors that occurs when inputting the data. This proposed software tool will read the software description, and will generate test patterns according to the input types and collects testing results, predicting the software reliability in real time and suggesting the possible ways to improve the software. For designing purpose PHP for web application will be used to give the testing results.

Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays

The statistical delay of a path is traditionally modeled as a Gaussian random variable assuming that the path is always sensitized by a test pattern. Its sensitization in various circuit instances varies among its test patterns and the pattern induced delay is non-Gaussian. It is modeled using probability mass functions (PMFs). This article presents an automatic test pattern generation (ATPG) method, where multiple uncorrelated test patterns per path improve its defect coverage (DC). The impact of the ATPG process is evaluated by comparing to traditional methods. It is also shown that the presented ATPG is useful in selecting critical paths.

Test Pattern Generator for MV-Based QCA Combinational Circuit Targeting MMC Fault Models

Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives for Integrated Circuit Technology considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology. Being at molecular scale, defects are more likely to occur in QCA devices. Therefore, the substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. This paper addresses the fault model caused by multiple missing cells defect and test generation for these faults for QCA circuits. We have shown that the single missing cell considerations are not enough. Correspondingly, in this paper, testing properties for the detection of fault caused by multiple missing cell defects in QCA devices mainly Majority Voter (MV) are proposed. Even though there are many advanced ATPGs available for CMOS technology, to demonstrate very special MV-based properties with reference to the test pattern generation process and to open the path for advanced combinational and sequential ATPGs specific to MV-based QCA circuits, the extension of basic Automatic Test Pattern Generator is proposed here. The proposed test generation algorithm is guided by the extended Sandia Controllability Observability Analysis Program (SCOAP) testability measures especially for QCA logic primitives.

BIST for Reconfigurable System on Chip (SOC) for Micro-Vibration Measurement

This paper presents methodology for testing mixed signal circuits in the SOC configured for micro vibration measurement. The SOC for micro vibration measurement contains a Bi morph sensor and front end electronics containing an amplifier, peak detector interface with A/D converter and memory. The amplifier is tested by applying triangular stimuli input generated by Test Pattern Generator (TPG) configured in the FPGA. The peak detector is tested by applying a test pulses generated by test generator system. The outputs of the test circuit are analyzed by output response analyzer (ORA) in the FPGA. The required hardware for testing analog as well as digital circuits of the SOC are configured by the on chip portion of FPGA and FPAA. The whole SOC can be tested by applying stimuli generated in TPG and checking the output by comparing patterns stored in memory with reference pattern using ORA. Simulation results are reported for counter and test ADC.

RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing

Software-based test (SBST) techniques are increasingly being used for testing of modern processors because of the ease of synthesis using evolutionary approaches, coverage for difficult to test faults, non-intrusive nature, low hardware overhead, etc. However, the test synthesis time required by SBST is high. In this paper, an advanced SBST technique, termed as Rapid SBST (RSBST) is proposed that reduces the overall test synthesis time by reusing the simulation responses of existing test programs of identical observability. The test codes, developed using the evolutionary process, that produce similar fault simulation results are reused for the fault evaluation. We exploit this reusability to enhance the speed of the test synthesis process. The efficacy of the proposed scheme is demonstrated on a 32-bit MIPS processor and on a minimal configuration of 7-stage SPARC V8 Leon3 soft processor. The traditional SBST synthesis requires 122 hours for the MIPS processor and 142 hours for the Leon3 processor to develop test program sets that cover 93.9% and 92.9% of the behavioral-level faults of these processors, respectively. An existing enhanced greedy-cover method, that also detects the hard-to-test faults, improves the coverage towards 96.3% for the MIPS processor and 95.8% for the Leon3 processor, but this slower test development consumes 168 hours and 172 hours, respectively. In the proposed RSBST scheme, the synthesized test codes achieve an adequate fault coverage of 96.1% for the MIPS processor and 95.5% for the Leon3 processor. This accelerated test pattern generation takes 90 hours and 98 hours for these two processors. So it may be concluded that the proposed RSBST technique speeds up the traditional SBST synthesis by a factor of 1.35 while maintaining the fault coverage above 95.5%. To validate the test quality evaluation using behavioral fault models, a strong correlation (94.8%) between the behavioral faults and gate-level faults of MIPS processor is demonstrated and verified for the proposed RSBST scheme. Also, the simulation responses of the test programs synthesized by RSBST scheme consumes only 14.25% of storage space when compared with the storage consumption of the actual simulation used by the existing test code generation methods.

Generation of Reduced Test Vectors for Multiple Stuck at Faults using Genetic Algorithm

As seen in the fabrication of circuits faults free circuits are difficult to obtain, as the manufacturing process is narrowing down, hence finding faults is very essential at the design level to obtain fault free circuits. As seen many of circuits have single and multiple faults, as known many research has been carried out to generate test pattern set that detect MSA faults, here the proposed ATPG method makes use of test patterns of single stuck at faults to identify MSA faults. This paper implements a method for multiple faults, generated test patterns for multiple faults has proved to be efficient by adapting a complex method of the order 3n-1 for ‘n’ lines reduced test pattern sets were obtained. This method overcomes the limitations of continuous searching algorithms, as the initial value of population size was randomly set to produce test vectors for MSA faults. The CPU processing time is very less compared to other ATPG techniques. To understand the working of the proposed methodology, we have performed an analysis by considering the ISCAS Benchmark circuits, to which the proposed ATPG method is applied, which gives the complete test vector (pattern) generation for MSA faults in the limited interval of runtime which also covers the test pattern sets for single faults.

New Hybrid-Based Self-Test Strategy for Faulty Modules of Complex Microcontroller Systems

In this paper, a new hybrid test strategy, called hybrid-based self-test (HYBST), is presented to test complex digital circuits such as microcontrollers. This test strategy integrates the signature multi-mode hardware-based self-test (SM-BST) with the software-based self-test (SBST). In this test strategy, the microcontroller is divided into a number of main modules, and then test subroutines are used to functionally test each module, based on its instruction set architecture (ISA). The ISA is used to generate test subroutines that represent test pattern generators (TPGs) and part of the test controller. The SMHBST represents the other part of the test controller and the test response compaction (TRC). The experimental results illustrate the superiority of the HYBST in the memory utilization, test application time, testing of internal modules of the microcontroller, and testing of general-purpose input-output (GPIO) pins of the microcontroller. In addition, an integrated test solution for fault diagnosis of the circuit boards including random logic integrated circuits (ICs) and microcontroller chips is presented to indicate a real practical test strategy.

Test pattern generation using thermometer code counter in TPC technique for BIST implementation

This paper introduces a newly pattern generation with Test-Per-Clock technique for Built-In-Self-Test implementation. This proposed test vector generation generates Multiple Single Input Change vectors. Each pattern enforced in SIC vector as scan chain. To generate minimal transition sequence of test patterns, a scalable SIC counter and Thermometer Code Counter implemented. The proposed Multiple SIC vector generator is adaptable to both Test-Per-Scan, Test-Per-Clock techniques. This method developed a theory to evaluate MSIC scheme. Survey outcome demonstrates that, applying Multiple SIC test patterns on ISCAS C432 benchmark reduces the power consumption due to uniform distribution and lesser transition generated test patterns.

A Model based Test Pattern Generation and Testing Framework for IoT Applications

The whole world is entering towards the trend of smart technology. Internet of Things ( IoT) is an important domain behind this enormous growth. A simple IoT system consists of a device or actuators or sensors, which are connected to software with the help of an internet. The embedded sensors can be monitored and managed from remote place through the network from anywhere in the world internet. There are various applications that are supported in this domain due to this feature. They are smart agriculture, Home automation, been applied in various domains like Home automation, Patient Health Monitoring, Smart City, Smart Agriculture and much more. The usage of these applications is increasing day by day, so there arises a need for verifying and validating the IoT devices in all aspects. The test automation framework that generates test pattern for various testing of IoT application domains that deploys in a sequence process of test patterns which can be easily started for the development of IoT scenarios described. To test their IoT device, there is a need for proper testing techniques for IoT applications through different IoT developers follow their own strategy. The main goal of the automation framework is to reduce the effort in the testing process and to make the test process easier for testing the IoT applications by generating various test patterns various tests depends on a number of IoT test patterns, which allows the process of various operations as the future extension.

An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction

This paper proposes an efficient diagnosis-aware automatic test pattern generation (ATPG) procedure that can quickly identify equivalent-fault pairs and generate diagnosis patterns (DPs) for nonequivalent-fault pairs, where a (non)equivalent fault pair contains two stuck-at faults that are (non)equivalent. The proposed procedure contains three main methods, which together can efficiently generate highly compacted DPs by using a conventional ATPG tool. First, an all-pairs at-a-time diagnosis pattern generation (AFPAT-DPG) method, which adopts user-defined fault models (UDFMs), is employed to quickly generate DPs for most fault pairs that cannot be distinguished by a given set of, typically fault detection, test patterns (TP). For those fault pairs that cannot be distinguished by AFPAT-DPG, a multipair diagnostic ATPG method (MP-DATPG) is used. MP-DATPG is a complete method in the sense that it can generate diagnosis tests for every distinguishable pair of faults or prove that the pair of faults is indistinguishable. However, due to back-track limits in test generation procedures, diagnosis test generation for some fault pairs may be aborted after the application of the two methods. For such fault pairs, a subcircuit analysis (SCA) method is applied to identify equivalent fault pairs among the aborted fault pairs by trimming the circuit under consideration into one that is much easier to process within the back-track limits of the test generation procedures. Experimental results show that the proposed procedure is the first work that distinguishes 100% of all fault pairs in all ISCAS’89 and IWLS’05 benchmark circuits and over 99.99% for all ITC’99 benchmark circuits using a conventional ATPG tool that generates tests to detect faults.

Implementation and Utilization of LBIST for 16 bit ALU

This paper refers to implementation of Low Power Built-In-Self-Test (LBIST) and its utilization for testing of 16 bit ALU core. Low Power Test Pattern (LP) Generator is programmable and able to produce pseudorandom test patterns. The programmability feature brings in selectiveness in toggling levels of test patterns. This helps to increase the error coverage gradient. This low power pattern generator consists of a pseudo random pattern generator (PSPR) which can be a linear feedback shift register or ring generator. The test pattern generator allows the production of binary sequences by devices with that selected toggling rate is defined as ‘Preselected toggling’ (PRESTO) activity. In this methodology, controls for operation of generator are selected automatically. Selection of all the controls is made simple and accurate for the tuning. Using this method fault coverage of test pattern generator can be improved as well as pattern count ratio gets improved. The proposed low power test compression method helps to get predictable test patterns. Here preselected toggling based logic BIST is used to get flexible and accurate test patterns hence high quality testing is achieved here with integration of PRESTO and LBIST method.

Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs.

Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose

We introduce a methodology for identifying worst case test vectors (WCTVs) for delay failures induced by total dose in sequential circuits implemented in flash-based field-programmable gate arrays (FPGAs) using design-for-testability (DFT) techniques and path delay faults using commercially available DFT and automatic test pattern generation (ATPG) tools. We verified this methodology experimentally using Microsemi ProASiC3 FPGAs and Cobalt 60 facility. The experimental results show a significant impact on the total dose failure level when using WCTVs in total-dose testing of FPGA devices.

Low-power design-for-test implementation on phase-locked loop design

Low-power design for test is the need of the hour for any system-on-chip designer. The low-power design techniques have been a major challenge to both the designer as well as the testing engineer. With so many advancements in low-power technology in the phase of register transfer logic design, functional verification, register transfer logic and physical synthesis and physical design. Design for test is not an exception to this. The low-power design-for-test techniques can be applied at various levels of the design-for-test flow as in the scan insertion stage, automatic test pattern generation simulations stage, testing stage, and so on. Some of the reasons for the high-power utilization in the design-for-test phase can be due to the external circuitry being inserted during the design phase and not used in the functional mode. The complete circuit will be active in the test mode only. In this paper, the focus will be primarily on reducing the power during the automatic test pattern generation scan synthesis phase. All the scan flops are connected by a common scan clock with a fixed frequency. The intention of this study is to divide the clock frequency by half and make sure that the power is reduced without affecting any timing violations. Since the scan clock frequency is low, it can be further divided to ensure that power is reduced without affecting the testing process of the chip.

Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions

Recently there has been a growing interest in the applicability of reversible circuits. Reversible circuits are designed using reversible gates, which can efficiently reconstruct the previous state of the computation from the current state. These circuits may find potential applications to the future generation of optical and quantum computers. To ensure the reliability of these circuits, testing is a mandatory phase of the design cycle. Several fault models have been introduced for reversible circuits among which some of them have been taken from the conventional circuits. In this paper, we consider the problem of testing bridging faults (such as single and multiple input bridging faults, single and multiple intra-level bridging faults) in a reversible circuit designed with the NOT, CNOT, Toffoli gates (NCT library) and generalized (n-bit) Toffoli gates (GT library). We propose an Automatic Test Pattern Generation (ATPG) method using the Path-Level expression for generating the minimal complete test set to detect the faults mentioned above. The analysis of the experimental results shows that the proposed method has 100% fault coverage, and test set size is smaller than the existing methods.