Test Pattern Generation Research Articles

A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture

A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra $0.13~\mu \text{m}$ process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs.

A comparative analysis of bio-inspired optimization algorithms for automated test pattern generation in sequential circuits

In recent years, bio-inspired optimization algorithms have demonstrated the ability to produce optimal solutions to numerous complex computational problems in science and engineering. In this work, a comparative analysis of bio-inspired algorithms is presented to understand and quantify the performance of algorithms in guiding the search process toward better solutions over all feasible solutions. Three evolutionary algorithms, namely, the Genetic Algorithm (GA), Particle Swarm Optimization (PSO) and Differential Evolution (DE), are implemented to generate an optimized test sequence set for digital sequential circuits to investigate how they explore and the exploitation realized in their search spaces. The merit of using a comparative method to analyze and optimize search spaces is to reach a reliable and quantifiable conclusion about the relative performance of each algorithm.An improvement in the quality of solutions was achieved, particularly in terms of testing time, number of test vectors, and fault coverage of tested sequential circuits in comparison with other algorithmic test generators that have been presented in the literature. The study shows how to effectively reduce the search space without negatively affecting the results and guides the search process over a large space. In addition, the experiments highlight the limitations of each optimization algorithm and offer some constructive methods of improvement. Moreover, several recommendations and guidelines regarding the use of optimization algorithms as test pattern generators to improve their performance and increase their efficiency are presented. Finally, we emphasize the relevance of bio-inspired algorithms in solving complex computational problems, data manipulation, and optimization objectives.

Optimized counting threshold Built-in redundancy analysis for memories

Memory plays pivotal roles in any System on chip (SOC) design. While manufacturing the memories, there may be a chance of defects in the memory so it will influence its total yield. So, it is necessary to ensure the defect less memory while manufacturing itself. There are certain techniques like the Built-in self-test (BIST) to test the working condition of the memory in the chip itself. If the memory is repairable then it will not affect the total yield. There are repairing mechanisms such as Built-in redundancy analysis (BIRA), which can be used to repair the memory in the chip itself. In this paper, we propose anoptimized Built-In Redundancy analysis algorithm, which uses Customized Fibonacci Based Test Pattern Generation (CFBTPG) and optimized counting threshold logic for testing and repairing analysis.The proposed method shows better results in comparing with the existing counting threshold algorithm and commonly used Comprehensive Real-time Exhaustive Search Test and Analysis (CRESTA) algorithms.

Power Optimization by Using Reconfigurable LFSR with Gated Clock

LFSR are the most commonly used test pattern generators due to its efficiency than any binary counters. This paper presents the design of a novel reconfigurable LFSR with clock gating for VLSI testing. The technology advancement in VLSI has increased the complexity of chip testing. This complexity in testing has made the Logic BIST (LBIST) more popular than Automatic Test Equipment. This helps the testing with an additional hardware added inside the circuit. ATE does not apply any test patterns but the test patterns are generated by the testing circuits which are inbuilt in the hardware. Thus the cost of testing is greatly reduced. In the LBIST, reconfigurable LFSR are used for the test pattern generation which improves the fault coverage in IC testing. This increases the generation of random test pattern. To increase the speed of testing and reduce the power required a clock gating is introduced in the reconfigurable LFSR. In traditional testing more transistors are required in the circuits resulting in consumption of more power than power required for the functioning of the circuit. Conventional clock circuit consumes 70% of the clock buffer. This reduces the number of switching activities in the BIST. The power consumption of the proposed reconfigurable LFSR with gated clocking is significantly reduced when compared with the conventional LFSR with clocking circuits.

Adaptive random testing with total cartesian distance for black box circuit under test

<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Single stuck-at-faults detection using test generation vector and deep stacked-sparse-autoencoder

This paper proposed a new method for testing digital circuits without hardware implementation. This data-based method detects hundreds of single stuck-at faults in the ALU circuits, utilizing deep stacked-sparse-autoencoder (SSAE). ATALANTA software is one of the free automatic test pattern generation tools which cover faults in high accuracy. Test vectors which are extracted from bench circuits via ATALANTA software are the key point of the paper. Fault detection is introduced as a two-class problem. SSAE network is trained using the test vectors. Dimension reduction is done automatically in SSAE. Network performance is tested by changing sparse coefficients, number of stacked autoencoder and data augmentation. The results of this step are compared with the traditional multilayer perceptron classification. In this method, unlike SSAE, a manual method of reducing the dimension and extracting the feature is used. Fault coverage of ATALANTA software is over than 94%. Finally, the results obtained from the deep neural network show its significant performance in the circuit faults detection automatically.

An Effective and Efficient Automatic Test Pattern Generation (ATPG) Paradigm for Certifying Performance of RSFQ Circuits

Rapid single flux quantum (RSFQ) logic, based on Josephson junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of complementary metal-oxide-semiconductor (CMOS). Due to its use of fabrication processes with large feature sizes, the defect density for RSFQ is lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific nonidealities are major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly distorted pulses are interpreted logically correctly by cells, but the timings are affected. Therefore, timing verification and delay testing increase in importance in RSFQ. Our goal is to ensure that designs and fabricated chips provide desired performance. To achieve this goal, we propose new methods and tools for timing verification and delay testing of fully path balanced RSFQ logic circuits that use concurrent-flow clocking scheme. We address several radically new phenomena in the RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by timing violations due to process variations. We then propose a completely new paradigm for automatic test pattern generation (ATPG) which utilizes these new phenomena to select multicycle paths as targets and to generate test patterns that are guaranteed to excite the worst-case delay along each target multicycle path. Finally, we present theoretical proofs and Monte Carlo simulation results for benchmark circuits under process variations to demonstrate that the patterns generated by our new ATPG are effective (invoke maximum delays of target multicycle paths) and efficient (require small numbers of patterns).

Graph‐based approach towards hardware Trojan vulnerability analysis

The author proposes an incremental windowing technique based on graph technique to detect hardware Trojan triggering signal. First, they analyse the switching activity file generated during simulation. Then, based on the window size of choice, they extract paths of n-HT (n-hardware Trojan; n is the number of triggering signals) and compare the path information with the HT instances from HT database to determine HTs' earliest/farthest activation time. They experiment with the incremental windowing technique on 420 combinational HT instances for four combinational designs. The results indicate that small and stealthy HT is active for a limited set of the time window and the number of test patterns during these windows is compact instead of exhaustive traditional random vector based Automatic Test Pattern Generation (ATPG).

Conversion Method of Netlists Consisting of Conventional Logic Gates to RSFQ Logic Circuits Utilizing Special RSFQ Gates

The conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to the netlists of RSFQ circuits, considering the reduction of the number of clocked gates, including D flip-flops (DFFs) for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer that can be utilized for realizing logic-or. The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. The detection methods of replaceable gates with those two kinds of gates are proposed. An automatic test pattern generation tool is utilized for detecting replaceable or gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering the cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and the assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU, and a 64-bit ALU. The evaluation results show that the number of clocked gates and the latency in the cycles of circuits is reduced by about 10%. The delay time of the converted circuits has been estimated and the reduction of delay overhead is discussed.

Efficient static compaction of test patterns using partial maximum satisfiability

Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation. Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains, including artificial intelligence, computational biology, data mining, and machine learning. We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation (ATPG) tool is redundant, and the relationship between test patterns and faults, as a significant information, can effectively induce the test patterns reduction process. Considering a test pattern can detect one or more faults, we map the problem of static test compaction to a partial maximum satisfiability problem. Experiments on ISCAS89, ISCAS85, and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

Defect-Oriented Test: Effectiveness in High Volume Manufacturing

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme

This brief presents a new test pattern generation scheme alongside a design for trust (DfTr) methodology for detecting hardware Trojan through side channel-based analysis approaches. The proposed scheme takes advantage of the proposed Hamming distance-based reordering and partition-based shuffling methods. The key idea behind the proposed work is that instead of distributing the circuit activity profile among all the nets with low transition probability at once, it can only be restricted to the smaller subsets of rare nets one at a time, while the rest of subsets remain at the lowest activity. As a result, a remarkable reduction in the background circuit activity by more than 41% and favorable enhancement of detection sensitivity about 31% are achieved compared to the state-of-the-art method.

VLSI Implementation of Linear Feedback Shift Register (LFSR) based Test Pattern Generator for Pseudo Exhaustive Testing

Advanced strides of improvement in programmable logic density, enhancements in speed and hardware description language (HDL) are empowering design engineers to implement highly performing and testable digital systems. Linear feedback shift registers (LFSR) are the critical elements in the testing and self testing of contemporary complex electronic systems like processors, Built-in-self-test (BIST) controllers and integrated circuits (ICs) etc. Fundamentally BIST is a Design-for-Testability (DFT) technique meant to configure testing functions physically with the circuit under test (CUT). To enhance the percentage of fault coverage as a part of BIST operations (testing the IC), LFSRs are deployed (as test pattern generator) to generate the test vectors inside logic BIST for testing digital systems. Proposed work is focused upon designing a fast adder based variable length pseudorandom binary sequence pattern generator (PRBSPG) and experimental validations. LFSR possess characteristics of high speed, better encoding efficiency, high fault coverage, low test volume data and low power consumption specially suitable in processing environment where uniform distribution random numbers are required. Verilog HDL is employed for structuring the modular design units while Xilinx ISE tool is deployed for validating the proposed LFSR design work and associated modular units.

Modern design approach of faults (toggling faults, bridge faults and SAT) of reduced ordered binary decision diagram based on combo & sequential blocks

In this Research we are going to develop ROBDD (Reduced Ordered Binary Decision Diagram) designs to detect toggling faults, bridge faults and SAT (Stuck at Fault), Here we are going to develop sequential blocks using ROBDD and applying to the mux to detect stuck at faults and also connecting the combo & Sequential blocks to find the toggling faults by connecting or using automatic test pattern generator. In this research we are going to develop the bridges between the blocks of ROBDD designs and converting them to and or logic to find the bridge faults of the design. Finding bridge and toggle faults are more difficult in logic designs, here we use an advance technique to find the faults of the design by calculating the path delays of the individual blocks of the design. More concentrating on the path delays by using basic stuck at faults methods to refer the faults (toggling and bridge faults) at mux output. In our research the basic design modules are ROBDD circuit of both combinational and sequential blocks are designed and tested using Multiplexer and K-map Simplification Methods. The main purpose of the research to find the faults at all levels of all logic designs which involves in both combinational and sequential blocks of the design.

HTDet: A clustering method using information entropy for hardware Trojan detection

Hardware Trojans (HTs) have drawn increasing attention in both academia and industry because of their significant potential threat. In this paper, we propose HTDet, a novel HT detection method using information entropy-based clustering. To maintain high concealment, HTs are usually inserted in the regions with low controllability and low observability, which will result in that Trojan logics have extremely low transitions during the simulation. This implies that the regions with the low transitions will provide much more abundant and more important information for HT detection. The HTDet applies information theory technology and a density-based clustering algorithm called Density-Based Spatial Clustering of Applications with Noise (DBSCAN) to detect all suspicious Trojan logics in the circuit under detection. The DBSCAN is an unsupervised learning algorithm, that can improve the applicability of HTDet. In addition, we develop a heuristic test pattern generation method using mutual information to increase the transitions of suspicious Trojan logics. Experiments on circuit benchmarks demonstrate the effectiveness of HTDet.

Maximal length test pattern generation for the cryptography application

Date security is the science and study of methods of protecting data in computer and communication systems from unauthorized disclosure and modification. With the introduction of hardware Trojans, data security becomes more critical. However Data security has evolved rapidly and have seen exciting developments in cryptography. Various algorithms are adopted for the data encryption and decryption processes for the higher level of security. Data is leaking by accessing the encrypted data over the medium of data transmission, so implementation of high security medium for data transmission has to be developed. Industries developing various techniques for verifying that programs do not leak confidential data. This paper explores a better understanding of the theoretical and practical limitations to security. By considering the pseudorandom property of cryptography, the Linear Feedback Shift Register (LFSR) based designs provides affordable intelligence security testing, facilitating their demand in VLSI chip design. It is analysed to generate maximal length random sequence to provide better cryptography. Pseudorandom sequence generator (PRSG) by LFSRs, encipherment and decipherment simulations are done using 180 nm CMOS process technology in ASIC flow, and validated using simulation results.

ANALYSIS OF DATA SKIPPING USING LOW TRANSITION SWITCH REGISTERS

The emerging scenario in the fields of VLSI testing has its own demand for fault diagnosis in VLSI circuits. If the area and size of the circuit increases the problem of test generation time becoming very tough. Efficient techniques for test generations are essential in order to reduce the test generation time and size. In Existing methods, Low transition Switch Register (LTSR) applies the corresponding repeated patterns of the generated test data. The complication in the LTSR technique exponentially increases power with respect to the circuit size. In case of circuit which has more stuck-at-fault, the LTSR method fails to provide suitable fault coverage and low power consumption. The proposed test data skipping scheme using Reconfigurable Johnson counter reduces the test data volume from the multiple test pattern and reduces switching transitions by skipping the test sequence mostly between the consecutive test sequences. The RJC based Test data skipping scheme has additional circuit which consists of various counters, Bit skipping circuit and logic gates. Memory unit consists of the whole test sequence then these test sequences are fed to RJC and Switching Transition counter. The consecutive test sequence are eliminated or skipped by comparing those counters and the state analysis of FSM. The proposed test data skipping scheme circuit is developed to achieve minimum test patterns and reduced scan power by skipping long scan chain switching activities. This present work with the above mentioned issues for LTSR and existing in VLSI circuits is to examine all detectable faults with proposed circuit. The Efficiency of such system is tested by Xilinx and ISE tools to generate test patterns to achieve high fault coverage with low power consumption over the conventional systems.

Design of Test Pattern Generator for Testing Crosstalk Faults in TSVs

Design of Test pattern generator to test crosstalk faults in Through Silicon Vias (TSV) in three dimensional integrated circuits presented in this paper. A well-known test pattern generation model for testing crosstalk called as Maximum aggressor fault model is adopted in the design. The finite state machine diagram for design of TPG presented in reference [1] is modified and the complete design of TPG is discussed in this paper. Verilog HDL Simulation and synthesis results of the proposed Test pattern generator is discussed.