Test Pattern Generation Research Articles

Innovative Multi-Bit Test Pattern Generators with Variable LFSR Selection Mechanisms

Test Pattern Generators is an important module for testing Asynchronous circuits that guarantee fault detection. In this paper a multi-bit TPGs with tunable LFSR lengths is presented. Our method enables smooth transitions between various word lengths by dynamically selecting LFSR configurations based on control signals. For 4-bit to 7-bit combinational circuits, we have derived a polynomial-based LFSRs and shown effect of stuck-at-fault detections through extensive testing. It includes a discussion of instructional insights regarding fault coverage and digital circuit design. By bridging fixed and flexible BIST solutions, our adaptive TPG design improves fault detection capabilities.

Automatic Test Pattern Generation for Robust Quantum Circuit Testing

Quantum circuit testing is essential for detecting potential faults in realistic quantum devices, while the testing process itself also suffers from the inexactness and unreliability of quantum operations. This article alleviates the issue by proposing a novel framework of automatic test pattern generation (ATPG) for robust testing of logical quantum circuits. We introduce the stabilizer projector decomposition (SPD) for representing the quantum test pattern and construct the test application (i.e., state preparation and measurement) using Clifford-only circuits, which are rather robust and efficient as evidenced in the fault-tolerant quantum computation. However, it is generally hard to generate SPDs due to the exponentially growing number of the stabilizer projectors. To circumvent this difficulty, we develop an SPD generation algorithm, as well as several acceleration techniques that can exploit both locality and sparsity in generating SPDs. The effectiveness of our algorithms are validated by (1) theoretical guarantees under reasonable conditions and (2) experimental results on commonly used benchmark circuits, such as Quantum Fourier Transform (QFT), Quantum Volume (QV), and Bernstein-Vazirani (BV) in IBM Qiskit.

Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models

Considering the scaling limitations of current Complementary Metal Oxide Semiconductor (CMOS) technology, Quantum-dot-Cellular Automata (QCA) is emerging as one of the alternatives. QCA being at the molecular scale, defects are more likely to occur in it. Therefore, substantial development of QCA-oriented defects, its corresponding fault models and test generation is required. In this paper, a test generation algorithm for a QCA combinational circuit is proposed. The FAN (A Fanout Oriented) test generation algorithm is extended for QCA. The proposed Automatic Test Pattern Generator (ATPG) for QCA targets Single Stuck at Fault (SSF) set produced by novel Multiple Missing Cells (MMC) defects. The proposed ATPG is based on the QCA-oriented test generation properties and guided by proposed testability measures.The MCNC benchmark circuits are synthesized into QCA using proposed synthesis algorithms to check the effectiveness of the proposed ATPG. The ATPG is developed using C++ and tested on MCNC benchmark circuits. Further, ATPG-generated test vectors are validated at the QCA device level to demonstrate their correctness. The QCADesigner-E tool is used for the device-level implementation of the MCNC benchmark circuit.

Comparative Analysis of 8-Bit Test Pattern Generator for LBIST

In order to guarantee their dependability, modern integrated circuits require efficient testing techniques. One of the greatest DFT methods [2] for logic design when an IC must be tested on a regular basis is LBIST. The DUT, a comparator, an analyzer, a test pattern generator, and memory for storing golden values are all part of the LBIST architecture. DUT affects the circuit's power because it dwells with the test circuitry. The use of area- and power-efficient TPG can lower this overhead. The project's primary goal is to put several TPGs that have been presented in a lifetime into practice and conduct a comparative analysis of them. Key Words: DFT, CUT, ORA, MC-LFSR, BSMCS, BS-LFSR, LP-TPG.

Test Power Reduction through Reordering Algorithm Implementation and Advancements in BIST Architecture

Due to the reduction in transistor size, test engineers face a severe issue in power minimization. VLSI circuit's power dissipation has become a vital concern due to the switching activity of the Circuit Under Test (CUT). Switching activity is a significant factor in determining power consumption for CMOS VLSI circuits. In this paper, we formulate a distance estimation technique and reordering using the Tversky index. Here, the distance between the test vectors is calculated using the Tversky index with the formation of an adjacency matrix, and reordering is performed. The experimental results of the proposed method have been compared to different distance measures and existing techniques. It shows that the switching activity is reduced from 52.5% to 21.5%, and the average power reduction is from 42% to 14.6% when the distance is estimated on reordering using the Tversky index measure. Thus, the Tversky index distance measure performs better than the Hamming, gray, and Linear feedback shift register (LFSR) methods. Switching activity estimation for complex ISCAS circuits has been performed and compared with existing methods for superior performance. We have also developed a Built in Self-Test (BIST) for the C17 benchmark circuit, which uses the Tversky counter as a test pattern generator using the TANNER EDA tool. Thus, an efficient deterministic BIST for the C17 benchmark circuit was designed to detect all the stuck-at faults, and the same procedure can be used to create BIST for all CUT and precomputed test sets for real-time field testing.

Applying Genetic Algorithm for test pattern generation process optimization

Applying Genetic Algorithm for test pattern generation process optimization

Finding the longest delay paths for the array-form multipliers using a genetic algorithm

Traditional digital multipliers are often designed in array forms or other variants. Timing of array-form multipliers can be analyzed by static timing analysis (STA), but the obtained timing result is conservative and pessimistic. Although statistical static timing analysis (SSTA) can partly solve the pessimism, it still does not generate test patterns for those near-to-longest delay paths. Finding near-to-longest delay paths can be helpful to designing error tolerant circuits, with which aggressive timing (with timing violation) can be exploited. In such design scenarios one should find test vectors to activate those near-to-longest delay paths in order to further run SPICE-precision diagnose on those potential timing violating critical paths. Test vector generation for such a testing problem is essentially an exhaustive enumeration problem when dealing with different forms of array multipliers. However, large size multipliers would result in an extremely large enumeration space for finding the longest delay path (LDP) test vectors. Currently there is no deterministic method that can guarantee to find test vectors for exact LDPs of a large size multiplier. Only very few research papers have addressed this problem, proposals are limited to heuristic methods without guarantee of finding the LDPs with the testing vectors. This paper investigates the potential of a genetic algorithm (GA) for searching the extensive test pattern space. By a fine design of GA, experimental running shows that a combination of well tuned evolutionary operators does empower the possibility of finding the LDPs for a set of moderate size carry-save adders (CSA) multipliers with the wordlength (WL) up to 25 bits on a plain laptop computer. Statistical properties of the proposed GA are examined.

Directed Test Generation for Hardware Validation: A Survey

The complexity of hardware designs has increased over the years due to the rapid advancement of technology coupled with the need to support diverse and complex features. The increasing design complexity directly translates to difficulty in verifying functional behaviors as well as non-functional requirements. Simulation is the most widely used form of validation using both random and constrained-random test patterns. The random nature of test sequences can cover a vast majority of scenarios, however, it can introduce unacceptable overhead to cover all possible functional and non-functional scenarios. Directed tests are promising to cover the remaining corner cases and hard-to-detect scenarios. Manual development of directed tests can be time-consuming and error-prone. A promising avenue is to perform automated generation of directed tests. In this article, we provide a comprehensive survey of directed test generation techniques for hardware validation. Specifically, we first introduce the complexity of hardware verification to highlight the need for directed test generation. Next, we describe directed test generation using various automated techniques, including formal methods, concolic testing, and machine learning. Finally, we discuss how to effectively utilize the generated test patterns in different validation scenarios, including pre-silicon functional validation, post-silicon debug, as well as validation of non-functional requirements.

Application of machine learning methods for automatic test pattern generation process optimization during circuit design

Application of machine learning methods for automatic test pattern generation process optimization during circuit design

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency

Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency

A survey of scan-capture power reduction techniques

With the advent of sub-nanometer geometries, integrated circuits (ICs) are required to be checked for newer defects. While scan-based architectures help detect these defects using newer fault models, test data inflation happens, increasing test time and test cost. An automatic test pattern generator (ATPG) exercise’s multiple fault sites simultaneously to reduce test data which causes elevated switching activity during the capture cycle. The switching activity results in an IR drop exceeding the devices under test (DUT) specification. An increase in IR-drop leads to failure of the patterns and may cause good DUTs to fail the test. The problem is severe during at-speed scan testing, which uses a functional rated clock with a high frequency for the capture operation. Researchers have proposed several techniques to reduce capture power. They used various methods, including the reduction of switching activity. This paper reviews the recently proposed techniques. The principle, algorithm, and architecture used in them are discussed, along with key advantages and limitations. In addition, it provides a classification of the techniques based on the method used and its application. The goal is to present a survey of the techniques and prepare a platform for future development in capture power reduction during scan testing.

FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment

Numerous security vulnerability assessment techniques urge precise and fast finite state machines (FSMs) extraction from the design under evaluation. Sequential logic locking, watermark insertion, fault-injection assessment of a System-on-a-Chip (SoC) control flow, information leakage assessment, and reverse engineering at gate-level abstraction, to name a few, require precise FSM extraction from the synthesized netlist of the design. Unfortunately, no reliable solutions are currently available for fast and accurate extraction of FSMs from the highly unstructured gate-level netlist for effective security evaluation. The major challenge in developing such a solution is precise recognition of FSM state flip-flops in a netlist having a massive collection of flip-flops. In this paper, we propose FSMx-Ultra, a framework for extracting FSMs from extremely unstructured gate-level netlists. FSMx-Ultra utilizes state-of-the-art graph theory concepts and algorithms to distinguish FSM state registers from other registers and then constructs gate-level state transition graphs (STGs) for each identified FSM state register using automatic test pattern generation (ATPG) techniques. The results of our experiments on 14 open-source benchmark designs illustrate that FSMx-Ultra can recover all FSMs quickly and precisely from synthesized gate-level netlists of diverse complexity and size utilizing various state encoding schemes.

Self-Test Library Generation for In-Field Test of Path Delay Faults

New semiconductor technologies for advanced applications are more prone to defects and imperfections related, among several different causes, to the manufacturing process, aging and cross-talks. These phenomena negatively affect the circuit’s timing and can be effectively modeled by means of the path delay fault (PDF) model. While path delay testing is currently supported by commercial Automatic Test Pattern Generation tools for scan designs, functional testing covering PDFs is not widely adopted, mainly because of the high cost for test generation. On the other side, functional test is already widely adopted for in-field test of stuck-at faults, which is often performed resorting to the execution of suitable test programs (Self Test Libraries, or STLs). This approach is attractive, since it can be performed at-speed with limited time constraints and high flexibility, making it a suitable in-field test solutions. Previous work assessed the feasibility and validity of functional approaches based on test programs targeting PDFs. In this work, we present the first systematic method for the development of very high fault coverage test programs for PDFs, which largely outperform test programs written for other fault models. Moreover, the proposed method allows the identification of functionally untestable faults. The effectiveness of the proposed approach was proven on an open-source RISC-V processor core, where 100% coverage of the functionally testable longest paths was achieved, compared with an initial coverage of 0.52% achieved with test programs targeting stuck-at faults. Results demonstrate that shorter paths are also effectively covered.

ASIC Implementation for Multiple Scan at Register Transfer Level

Design for testability (DFT) is introduced to reduce the complexity of testing integrated circuit and help improve fault coverage. However, conventional DFT with additional 2-to-1 multiplexer (MUX) might add an increasing amount of delay and area overhead. Therefore, register transfer level (RTL) scan design is introduced to overcome this problem. This paper aims to present the development of an ASIC with RTL scan design by using multiple scan paths instead of the conventional technique, which is gate-level (GL) scan insertion to insert scan cells. This method inserts multiple scan cells by utilizing the existing multiplexer and operational units in order to reduce area overhead and delay. Besides, multiple scan paths are implemented instead of a single scan chain to reduce the complexity of the testing process, where a single scan chain has long test application times due to the high number of clock cycles for the scan chain process. RTL design is also modified by adding an extra gate for multiple scan chain insertion. The graph is derived in order to analyse the connection between registers such that the multiple scan paths can be determined accordingly. Synopsys tool is used for synthesized, placement and routing and performing automatic test pattern generation while static timing analysis is used to verify the results of the setup slack time for ASIC design. The simulation result shows that multiple scan paths insertion at RTL level has an area overhead and slack time of about 3.79% and 0.44ns less compared to multiple scan paths insertion at GL for a finite impulse response circuit with comparable high fault coverage and small delay. A comparison of the performance metrics such as area, setup slack time, and fault coverage of the multiple scan chain is done between the RTL scan and GL scan.

Privacy Preservation Using Machine Learning in the Internet of Things

The internet of things (IoT) has prepared the way for a highly linked world, in which everything is interconnected, and information exchange has become more easily accessible via the internet, making it feasible for various applications that enrich the quality of human life. Despite such a potential vision, users’ privacy on these IoT devices is a significant concern. IoT devices are subject to threats from hackers and malware due to the explosive expansion of IoT and its use in commerce and critical infrastructures. Malware poses a severe danger to the availability and reliability of IoT devices. If left uncontrolled, it can have profound implications, as IoT devices and smart services can collect personally identifiable information (PII) without the user’s knowledge or consent. These devices often transfer their data into the cloud, where they are stored and processed to provide the end users with specific services. However, many IoT devices do not meet the same security criteria as non-IoT devices; most used schemes do not provide privacy and anonymity to legitimate users. Because there are so many IoT devices, so much malware is produced every day, and IoT nodes have so little CPU power, so antivirus cannot shield these networks from infection. Because of this, establishing a secure and private environment can greatly benefit from having a system for detecting malware in IoT devices. In this paper, we will analyze studies that have used ML as an approach to solve IoT privacy challenges, and also investigate the advantages and drawbacks of leveraging data in ML-based IoT privacy approaches. Our focus is on using ML models for detecting malware in IoT devices, specifically spyware, ransomware, and Trojan horse malware. We propose using ML techniques as a solution for privacy attack detection and test pattern generation in the IoT. The ML model can be trained to predict behavioral architecture. We discuss our experiments and evaluation using the “MalMemAnalysis” datasets, which focus on simulating real-world privacy-related obfuscated malware. We simulate several ML algorithms to prove their capabilities in detecting malicious attacks against privacy. The experimental analysis showcases the high accuracy and effectiveness of the proposed approach in detecting obfuscated and concealed malware, outperforming state-of-the-art methods by 99.50%, and would be helpful in safeguarding an IoT network from malware. Experimental analysis and results are provided in detail.

An exquisitely sensitive variant-conscious post-silicon Hardware Trojan detection

Hardware Trojans, malicious modifications or additions to circuit elements, are often introduced during outsourced stages of IC manufacturing. Their presence in hardware security platforms became a concern after incidents like the Syrian RADAR failure and the Kill-switch incident. Existing Trojan detection techniques mostly focus on netlist-level identification and overlook process variation challenges in post-silicon ICs. In this work, we introduce a novel golden free and highly sensitive detection method that addresses process variations and various sources of noise. Our approach achieves enhanced detection sensitivity by (i) utilizing an efficient circuit partitioning method that takes into account post-silicon noises, ensuring post-silicon validation through pre-silicon analysis, (ii) implementing a technique to mitigate the impact of systematic and random variations within and between dies, (iii) developing a variation-aware test pattern generation approach that utilizes a bit-flipping technique, leading to low transition net switching and increasing the likelihood of activating Trojans. We evaluate the sensitivity of our detection approach using a custom tool called relative power difference (RPD). To validate our method, we conduct experiments on the ISCAS’89 benchmark and the AES-128 circuit, testing against various Trojans reported in the literature. Our results demonstrate outstanding detection sensitivity for inserted Trojans across different levels of noise.

A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in [1], can determine the secret key efficiently, and break different logic locking schemes. In this paper, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generates one test pattern per fault. Second, we consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach can find test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults as well. We demonstrate the effectiveness of the approach on ITC'99 benchmarks. The results show that we can detect all the hard-to-detect faults and identify redundant faults and a 100% stuck fault coverage is achieved. In addition, we show that test generation time saving becomes significant for Approach 2 as multiple faults help reduce or remove conflicts.

Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration

Neuromorphic fabric based on emerging resistive non-volatile memories (NVMs) is a promising approach for the realization of Neural Networks (NNs) due to their low power consumption and latency based on in-memory computation. However, the non-idealities of NVMs shift activation distributions from training values, affecting post-mapping inference accuracy. Re-calibrating NNs’ batch normalization layer in a per-chip manner restores a shifted distribution close to the training distribution. However, re-calibration overhead is an issue not addressed in existing studies. Therefore, we propose approximate batch normalization and a test pattern generation method for efficient re-calibration. The proposed method requires only 0.2% of training data for re-calibration, but can regain 72.3% inference accuracy on various benchmark datasets and fault scenarios.

Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators

The proliferation of Deep Neural Networks (DNNs) in real-time mission critical applications has promoted the implementation of custom-built DNN inference accelerators. These accelerators require a considerable amount of on-chip memory to store millions of trained DNN parameters for executing inference at the edge. Drastic technology scaling in recent years have made these memory circuits highly vulnerable to faults due to various reasons like aging, latent defects, single event upsets, etc. Such faults are highly detrimental to the classification accuracy of the DNN accelerator, leading to the crucial Functional Safety (FuSa) violation. This can eventuate to catastrophic circumstances, when used in mission-critical applications. In order to detect such violations in mission mode, we propose to generate a set of functional test patterns by leveraging the concept of Generative Adversarial Networks (GANs), that are independent of the DNN model and the accelerator characteristics. Our experimental results demonstrate that, the generated test patterns significantly improve FuSa violation detection coverage by up to 130.28%, compared to existing techniques. To the best of our knowledge, this is the first work that generates GAN-based test patterns in order to perform FuSa violation detection in mission-critical DNN accelerators.

Testing and reliability enhancement of security primitives: Methodology and experimental validation

The test of security primitives is particularly strategic as any bias coming from the implementation or environment can wreak havoc on the security it is intended to provide. This paper presents how some security properties are tested on hardware security primitives including True Random Number Generation (TRNG), Physically Unclonable Function (PUF), and cryptographic modules. Moreover, we discuss how the sensors embedded to protect cryptographic modules against fault injection attacks should be calibrated over time to fulfill the requirement it was designed for. The testing we discuss in this paper is different from the conventional testing where we consider a fault model and generate test patterns via an ATPG to detect such faults. The test of TRNG and PUF to ensure a high level of security is mainly about the entropy assessment, which requires specific statistical tests. The security against side-channel analysis (SCA) of cryptographic primitives, like the substitution box in symmetric cryptography, is generally ensured by masking. However, the hardware implementation of masking can be damaged by glitches, which create leakages on sensitive variables. Accordingly, a test method is to search for nets of the cryptographic netlist, which are vulnerable to glitches. Finally, the Digital Sensor (DS) is an efficient primitive to detect disturbances and raise alarms in the case of fault injection attack (FIA). The dimensioning of this primitive requires a precise test to take into account the environmental variations including aging.This paper extends on a conference paper presented at DFTS’21 by the same co-authors, where the test methodology for three critical security primitives is presented. In addition, in this paper, we add experimental validation to show how such testing methodology is applied in practice.