Technology Computer-aided Design Research Articles

AI‐assisted Field Plate Design of GaN HEMT Device

AbstractGaN High Electron Mobility Transistors (HEMTs) plays a vital role in high‐power and high‐frequency electronics. Meeting the demanding performance requirements of these devices without compromising reliability is a challenging endeavor. Field Plates are employed to redistribute the electric field, minimizing the risk of device failure, especially in high‐voltage operations. While machine learning is applied to GaN device design, its application to field plate structures, known for their geometric complexity, is limited. This study introduces a novel approach to streamlining the field plate design process. It transforms complex 2D field plate structures into a concise feature space, reducing data requirements. A machine learning‐assisted design framework is proposed to optimize field plate structures and perform inverse design. This approach is not exclusive to the design of GaN HEMTs and can be extended to various semiconductor devices with field plate structures. The framework combines technology computer‐aided design (TCAD), machine learning, and optimization, streamlining the design process.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

Simulation of synaptic properties of ferroelectric memory capacitors and neural network applications

In this work, the electrical properties and synaptic characteristics of hafnium oxide-based ferroelectric memory capacitor with metal - ferroelectric layer - metal (MFM) structure were simulated using TCAD (technology computer aided design) software. Based on the synaptic potentiation/depression characteristics of the simulated memory capacitor, a multilayer perceptron (MLP) network was constructed, and the recognition accuracy and convergence speed of the MLP network in the MNIST recognition task were simulated, and the feasibility of the ferroelectric memory capacitor synaptic device for real neural network operation was analyzed. The results show that the recognition accuracy of the MLP network reaches 93% and stabilizes after 50 iterations of training, and the recognition accuracy of the MLP network is already at a high usable level after a smaller number of training times of 20, which suggests that the synaptic plasticity of the ferroelectric memory capacitor has a good potential for the practical application of the weight updating of the MLP network.

Self-bias Mo–Sb–Ga multilayer photodetector encompassing ultra-broad spectral response from UV–C to IR–B

Achieving an ultra-broad spectral response in a self-bias detector is a formidable challenge that persists in optoelectronics that necessitates innovative solutions. We propose a unique ultra-broadband photodetecting device, utilizing a multilayer structure comprising Molybdenum Di-sulfide (MoS2), Antimony Tri-selenide (Sb2Se3), and Gallium Nitride (GaN), which exhibits the unique capability of detecting photons without applied bias. The fabricated device demonstrates exceptional sensitivity to a wide range of illumination wavelengths, spanning from ultraviolet–C (UV–C) to infrared–B (IR–B). The design detector displays the highest photo-responsivity of 665 mAW−1 in photovoltaic mode and 3.89 × 105 mAW−1 in photoconductive mode. The designed detector also exhibits a minimal dark current of 90 nA and an extremely weak signal detection capability of ∼12 femto watt-hertz−1/2 at 6 V bias. Additionally, the thermal stability of the MoS2-Sb2Se3-GaN (Mo-Sb-Ga) multi-layer-based self-bias detector was explored. Under the self-bias conditions, the photodetector exhibits a stable behavior up to 250°C with a peak responsivity of 635 mAW−1. The thermal durability of the self-bias ultra-broadband photodetector indicates excellent potential for developing futuristic optoelectronic devices. Further, the performance of the developed detector was examined using Technology Computer-Aided Design (TCAD) simulations, providing valuable insights into the device behavior and the transport of photo-generated carriers, enhancing our understanding of the device operation and enabling performance optimization for diverse applications.

TCAD approach for negative capacitance ferroelectric devices for radiation detection applications

Negative capacitance (NC) emerges as a promising technology for low-power, high-performance transistors. The HiEnD project intends to analyze and design high-energy efficient electronic devices based on innovative ferroelectric materials. It explores NC technology for high-resolution tracking detectors in future high-energy physics experiments. It aims to create ultra-thin, radiation-resistant devices for superior signal detection in harsh environments. This paper presents detailed modeling, simulation results, and a comparison with experimental data, highlighting the potential of the developed methodology but also of the technology for the realization of compact, high-performance detectors. Advanced Technology CAD modeling has been employed to investigate the potentiality of NC devices in unconventional application domains, such as high-energy physics experiments. Numerical simulations, capable of verifying experimental results, enhance predictive power, reducing time and cost in detector design and testing.

Measurements and TCAD simulations of guard-ring structures of thin silicon sensors before and after irradiation

The developing of high performing silicon detectors for particle tracking in the next generation of high-energy physics experiments at future colliders (e.g., HL-LHC, FCC) able to operate efficiently up to very high fluence (∼1⋅10171MeVneq/cm2) is of the utmost importance. In order to sustain high voltage values with minimum leakage current injection into the core region of the sensor, the design and optimisation of the Guard-Ring (GR) protection structure is crucial, especially when small substrate thicknesses are used. In a recent R&D batch produced at Fondazione Bruno Kessler (FBK) in the framework of the “eXFlu” project - INFN CSN5 grant for Young Researchers, different optimisation studies of GR structures for thin substrates (45, 30, 20 and 15μm) up to high fluence (2.5⋅10151MeVneq/cm2) have been addressed. These have been enabled thanks to ad-hoc advanced Technology CAD (TCAD) modelling of different GR design strategies, accounting for the comprehensive bulk and surface radiation-induced damage effects, and an extensive test campaign on such GR structures, both before and after irradiation. In this paper the validation of the development framework of the various GR design options before and after irradiation is presented.

Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs

Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x1018 cm-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x1019 cm-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

(Invited) A Neural Compact Model Based on Transfer Learning for Organic FETs

Organic field-effect transistors (organic FETs) exhibit highly non-linear electrical characteristics due to their distinctive transport mechanism manifested by thermally-assisted hopping via localized states randomly distributed in both energy and space domains. This feature impedes the establishment of an analytical compact model. In this context, we present an approach to adopt artificial neural networks (ANN) for the development of a compact model, namely a neural compact model, by exploiting the powerful ability of the ANN to describe a non-linear function accurately. In addition, we evaluate the knowledge transfer method to reduce learning time and improve accuracy even when the data is scarce and costly. By technology computer-aided design simulation, we constructed a dataset of electrical characteristics of organic FETs with Gaussian disorder which is calibrated to the experimental measurement. Subsequently, we constructed and compared neural compact models based on conventional deep learning and transfer learning. We showed that the neural compact model with transfer learning provides an equivalent accuracy at a shorter modeling time. A complex dependence on the gate voltage, drain voltage, and temperature is successfully modeled over a wide range of operation regimes and temperatures.

Influence of annealing treatment on performance of 4H–SiC SBD irradiated by heavy ions under room temperature and low temperature

The influence of the annealing treatment on the performance of commercial 4H–SiC Schottky barrier diodes (SBDs) subjected to heavy ion irradiation under room temperature (RT) and low temperature (LT) are presented. Experimental results confirm that annealing treatment effectively eliminates defects and interface states caused by heavy ion irradiation, particularly for 4H–SiC SBD under LT irradiation. Increasing the annealing temperature leads to the slight improvement in forward current, leakage current and breakdown voltage. However, the annealing process may result in the formation of Ti and Si compounds at the interface between the Schottky metal and SiC, as well as a significant number of vacancies. Combined with Technology Computer Aided Design (TCAD) simulations, it is concluded that the interface trap charge concentrations exceeding 1 × 1012 cm−2 significantly impact the breakdown characteristics of 4H–SiC SBDs.

Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET

This research work evaluates a performance analysis of heterostructure (SiGe/Si) double gate extended source Tunnel FET (Hetero-ES-TFET) to enhance the analog performance, linearity and noise performance. At the source-channel junction, a Hetero-ES-TFET's source is extended into the channel to increase point and line tunneling in the device. The Hetero-ES-TFET exhibits a high ION/IOFF of 3.57 × 1012 and a maximum cut off frequency fT of 54.19 GHz for optimization of device structural parameters. This analysis is conducted using a calibrated SILVACO, technology computer-aided design (TCAD) simulator. The proposed structure includes evaluation of linearity and noise performance characteristics. Furthermore, a linearity analysis as a figure of merit was conducted for the proposed device under study, including different parameters such as 3rd order intermodulation distortion point (IMD3), 3rd order intermodulation intercept point (IIP3), 2nd and 3rd order voltage intercept point (VIP2 and VIP3). The proposed Hetero-ES-TFET has achieved an incredibly high ON current and low threshold voltage. The effect of increasing source width has been examined in this work while sub-threshold swing (SS) remains unchanged during the analysis. There is an improvement in threshold voltage and ION/IOFF value by using silicon-germanium (SiGe) as a source material.

Optimizing TCAD Model and Temperature-Dependent Analysis of Pt/AlN Schottky Barrier Diodes for High-Power and High-Temperature Applications

This research presents a comprehensive investigation and optimization of the Pt/AlN Schottky Barrier diode (SBD) using technology computer-aided design (TCAD) modeling. The study explores the electrical characteristics of AlN SBDs with various metal contacts, including Aluminum (Al), Silver (Ag), Tungsten (W), Gold (Au), Nickel (Ni), and Platinum (Pt). Through the comparative analyses of different metal/AlN Schottky contacts, the Pt/AlN structure emerges as the most promising due to its superior barrier height and lower leakage current. At [Formula: see text]K, the diode demonstrates a barrier height of 2.72[Formula: see text]V, a nearly ideal leakage current of 0.046[Formula: see text]pA, and a breakdown voltage of 363[Formula: see text]V. The research extends to examining the temperature-dependent electrical behavior of Pt/AlN Schottky diodes, particularly for high-power and high-temperature applications. Analysis carried out across temperatures ranging from [Formula: see text]K to [Formula: see text]K reveals a trend of increasing ON resistance and consistently lower leakage current with rising temperature. Importantly, the study indicates that the impact of temperature on the barrier height and breakdown voltage of the diode is negligible, thus rendering it suitable for high-temperature operation. Leveraging the unique properties of AlN as an ultra-wide bandgap material within the III-V compound semiconductor family, this research provides valuable insights into the potential applications of Pt/AlN Schottky contact. The study highlights that the Pt/AlN Schottky contact is effective not only for high-power, high-temperature SBDs but also as superior metal/semiconductor gate contacts for field-effect transistors (FETs). Their suitability is attributed to their ability to handle high voltages, minimize reverse leakage current, and demonstrate improved thermal stability.

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Energy-Performance Assessment of Oscillatory Neural Networks Based on VO2 Devices for Future Edge AI Computing.

Oscillatory neural network (ONN) is an emerging neuromorphic architecture composed of oscillators that implement neurons and are coupled by synapses. ONNs exhibit rich dynamics and associative properties, which can be used to solve problems in the analog domain according to the paradigm let physics compute. For example, compact oscillators made of VO2 material are good candidates for building low-power ONN architectures dedicated to AI applications at the edge, like pattern recognition. However, little is known about the ONN scalability and its performance when implemented in hardware. Before deploying ONN, it is necessary to assess its computation time, energy consumption, performance, and accuracy for a given application. Here, we consider a VO2-oscillator as an ONN building block and perform circuit-level simulations to evaluate the ONN performances at the architecture level. Notably, we investigate how the ONN computation time, energy, and memory capacity scale with the number of oscillators. It appears that the ONN energy grows linearly when scaling up the network, making it suitable for large-scale integration at the edge. Furthermore, we investigate the design knobs for minimizing the ONN energy. Assisted by technology computer-aided design (TCAD) simulations, we report on scaling down the dimensions of VO2 devices in crossbar (CB) geometry to decrease the oscillator voltage and energy. We benchmark ONN versus state-of-the-art architectures and observe that the ONN paradigm is a competitive energy-efficient solution for scaled VO2 devices oscillating above 100 MHz. Finally, we present how ONN can efficiently detect edges in images captured on low-power edge devices and compare the results with Sobel and Canny edge detectors.