Technology Computer-aided Design Research Articles

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Investigation on electrical parameters between single and double material gate nanoribbon FETs including trap distributions

The presence of multiple interface of gate-oxide and semiconductor in Nano-ribbon FET (NR-FET) causes several defects and leads to the degraded electrical parameters. In this regard, the electrical parameters in the existence of interface trap charges (ITCs) for single material gate (SMG) and double material gate (DMG) NR-FETs are extracted using Technology Computer Aided Design (TCAD) simulator. The effect of Uniform/Gaussian ITCs at the oxide and semiconductor interface on drain current, electrostatic potential, ON current, OFF current, and threshold voltage are reported for these devices. The RF/analog performance like transconductance (gm), gate capacitance (Cgg), and cut-off frequency (fc) are reported for these structures in presence of non-ideal trap distributions. Moreover, the linearity parameters like higher order harmonics in gm (gm2 and gm3), voltage intercept points (VIP2 and VIP3), input intercept power (IIP3), and intermodulation distortion (IMD3) are highlighted for these structures. It is seen that DC, RF/analog, and linearity performance of both the NRFETs are significantly affected by Uniform and Gaussian distribution of ITCs. However, the electrical parameters in DMG NRFET is more immune to ITCs than SMG NRFET. Moreover, both the devices have ON state current in the order of 10−3 A, fc of order THz, and improved linearity behaviour in the presence of ITCs, which indicates sustainability of these devices including ITCs.

Two- and Three-Dimensional Recrystallization of Discrete Amorphous in C3H5-Molecular-Ion-Implanted Silicon Surface Analyzed by TCAD Simulation

Technology computer-aided design (TCAD) kinetic Monte Carlo simulations revealed the unique recrystallization processes of discrete amorphous regions connected to a buried amorphous layer in a C3H5-molecular-ion-implanted silicon (Si) substrate. The faithful simulation models show that the discrete amorphous regions are first recrystallized two-dimensionally in the lateral direction from both sides and separated from the buried amorphous layer. Then, the separated discrete amorphous regions are recrystallized three-dimensionally in the lateral and vertical directions from both sides and the bottom. We found that the first two-dimensional recrystallization of discrete amorphous regions is caused by the retardation of solid-phase epitaxial growth at the Si substrate surface and near the buried amorphous layer. We also found that the large (small) discrete amorphous regions require a long (short) two-dimensional recrystallization before separating from the buried amorphous layer. The transition point in the recrystallization dimension can be determined from the lateral recrystallization length and the equivalent radius of discrete amorphous regions.

A 3-D GaAs-based Hall sensor design with dual active layers structure

A fully integrated 3-D Hall magnetic sensor with dual active structure was proposed. Results by technology computer-aided design simulation show that the proposed sensor provides a doubled magnitude improvement in sensitivity of vertical magnetic field direction and maintains a good level sensing of horizontal magnetic field direction compared with the sensor with single active layer. The designed sensor was fabricated by wet etching process and a method of preparing Ohmic contacts on the "pseudo-sidewalls" is proposed. The measurements show that the non-linearity does not exceed 0.5% and a voltage sensitivity of up to 0.046 T−1, which matches the simulation results. The proposed sensor boasts a simplified structure that allows for fabrication using different layers only through a planar process, which makes it more conducive to the integration of devices and systems.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference.

Cd0.2Zn0.8O nanowire thin film transistor for low kickback high-speed AMLCD circuit applications

This paper reports the Cd0.2Zn0.8O channel cylindrical gate-all-around nanowire thin-film transistor (CY-GAA-NWTFT) for high-speed active-matrix liquid crystal display (AMLCD) pixel circuit with minimal kickback voltage. The AC/DC, analog, and energy efficiency of this device are investigated against the variation in lateral (channel length) as well as vertical dimension (oxide thickness) using technology computer aided design (TCAD) device simulation environment. Further, the behavior of CY-GAA-TFT is crosschecked by implementing it on resistive load digital inverter circuit followed by transient analysis to calculate delay of the inverter circuit. Moreover, static analysis has been also performed to evaluate its voltage transfer curve (VTC) to derive its noise margin and voltage gain. The execution of the proposed CY-GAA-NWT device on AMLCD pixel circuit indicates tremendous improvement in performance in terms of high-speed applications and low kickback voltage.

Mole Fraction and Device Reliability Analysis of Vertical-Tunneling-Attributed Dual-Material Double-Gate Heterojunction-TFET with Si0.7Ge0.3 Source Region at Device and Circuit Level

This paper puts forward a new vertical-tunneling-attributed dual-material double-gate heterojunction-TFET (VTDMDG-HTFET). The device structure of VTDMDG-HTFET includes Si[Formula: see text]Ge[Formula: see text] material for the designing of source region. The mechanism of vertical tunneling in VTDMDG-HTFET provides superior electric field at tunneling interface and leads to improved transfer characteristics. VTDMDG-HTFET also includes metal gate work-function engineering approach to facilitate high ON-current and small OFF-current. Application of high-[Formula: see text] dielectric material HfO2 in the form of gate oxide enhances the capacitive-coupling at channel-source interface. Moreover, the work includes the comparison of proposed VTDMDG-HTFET with the conventional vertical-tunneling based dual-material double-gate-TFET (VTDMDG-TFET). It has been observed from the simulation results that SiGe source-based VTDMDG-HTFET offers better DC characteristics in terms of superior ON-current, smaller OFF-current, steeper subthreshold-slope, lower threshold voltage, higher transconductance along with smaller drain-induced barrier-lowering (DIBL) effects as compared to its counterpart silicon-source-based VTDMDG-TFET. In this work, reliability of VTDMDG-HTFET has also been examined and compared with VTDMDG-TFET in terms of temperature sensitivity and effect of different interface trap charges. The device simulation and investigations have been carried out using technology computer aided design (TCAD) tool. Moreover, device circuit mixed-mode simulation analysis is carried out for conventional and proposed device based resistive load inverters. A comparison is performed between both the inverters in terms of prorogation delay and switching threshold voltages. Further, the mixed mode simulation analysis is also performed for the proposed device based inverter under the influence of different interface trap charges (ITCs). Study shows that reliability performance of the proposed device is better as compared to its counterpart conventional device. Hence, vertical tunneling and SiGe source-based VTDMDG-HTFET can be a better choice for various applications such as analog/RF, analog and digital electronic circuits, energy harvesting, gas-sensing and memory devices.

Simulation Research on High-Voltage β-Ga2O3 MOSFET Based on Floating Field Plate

The simulation model of a depletion-mode (D-mode) β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) is constructed by Silvaco ATLAS technology computer-aided design (TCAD) simulation, which employs an epitaxial drift layer grown on a sapphire substrate. On this basis, the floating field plate (F-FP) structure based on the gate-pad-connected field plate (P-FP) is proposed to improve the breakdown characteristics of the device, which is easy to be prepared. The working principle of F-FP is investigated with the help of the device with one F-FP. Based on the principle that the number of floating field plates is increased on an optimized floating field plate structure. Subsequently, the devices with two and three floating field plates are simulated in turn, and the optimal structural parameters of the three F-FPs device are finally obtained, and the breakdown voltage is 3800 V at this time. In addition, it is found that the device breakdown voltage is increased by approximately 500–600 V for each additional floating field plate.

High‐Frequency fT and fmax in Organic Transistors: Performance and Perspective

AbstractIn state‐of‐the‐art organic transistors, the transit frequency fT is reported to be fT = 40 MHz for vertical organic transistors, where a voltage‐normalized fT corresponds to 0.36 MHz V−2. The reported highest fT for conventional organic transistors is fT = 160 MHz, where the voltage‐normalized fT is 0.1 MHz V−2. While the reported transit frequency fT of n‐MOSFETs for silicon technology when normalized by the applied biases exceeds 300 GHz V−2. The reported carrier mobility of organic semiconductors is over 100 cm2 V−1 s−1, which is almost an order of magnitude lower than that of silicon. However, the transit frequency fT of organic transistors lags far behind silicon technology by about six orders of magnitude at a comparable device length below 300 nm. In this work, a technology computer‐aided design (TCAD) simulator is adjusted to the experimental DC and AC characteristics of the 200 nm device length vertical organic permeable‐base transistors (OPBTs) based on C60 as semiconductor. The AC performance of the devices is investigated and quantitatively analyzed the influence and contribution of key design, structure and material parameters that determine fT and fmax. The feasible ways to enhance and optimize the highest achievable fT and fmax are identified to reach the and overcome the limitations to high‐frequency operation in organic transistors.

A design TCADAS tool for semiconductor devices and case study of 65 nm conventional floating-gate MOS transistor

An automatic programming tool has become an essential component in virtual fabrication in recent years. This paper aims to propose a methodology of virtual fabrication for semiconductor devices and design a tool called Technology Computer-Aided Design Automatic Simulation (TCADAS) which can perform a completely virtual fabrication, device simulation, process variation, and output extraction. Especially, the TCADAS tool eliminates drudgery when studying semiconductor devices such as complexity in setting inputs, substantial manual work, and long run time of simulations. This work investigates the completed flow for a 65 nm conventional Floating-gate MOS transistor as a case study, which is widely considered a vital determinant of the non-volatile memory field. A detailed automatic process from the entry to a completed three-dimension structure, device characterization, extract important output parameters such as memory window, ION/IOFF, Gate Coupling Ratio (GCR), and speed operations are presented. The TCADAS tool was designed by Python language and the utilities of TCAD Silvaco tools including Athena, Atlas, and DevEdit3D.

TEM Image Analysis and Simulation Physics for Two-Step Recrystallization of Discretely Amorphized C3H5-Molecular-Ion-Implanted Silicon Substrate Surface

In this study, we investigate the initial rapid recrystallization of a discretely amorphized C3H5-molecular-ion-implanted silicon (Si) substrate surface in the subsequent thermal annealing treatment through the analysis of plan-view transmission electron microscopy (TEM) images and technology computer-aided design (TCAD) process simulation. In the approach of the analysis of the plan-view TEM image of the Si substrate surface, we found that initial rapid recrystallization occurs in the intermediate regions between the residual crystalline and discrete amorphous regions formed in the C3H5-molecular-ion-implanted Si substrate surface. In addition, the TCAD process simulation results indicate that the intermediate regions correspond to the amorphous pockets formed around the discrete amorphous regions in the C3H5-molecular-ion-implanted Si substrate surface and are recrystallized preferentially during the short thermal annealing time. These plan-view TEM image analysis and TCAD process simulation results reveal a two-step recrystallization of the discretely amorphized C3H5-molecular-ion-implaned Si substrate surface. After the initial rapid recrystallization of amorphous pockets in the 1st step, the recrystallization of discrete amorphous regions starts in the 2nd step. The incubation period between the 1st and 2nd steps is the time required to recrystallize the amorphous pockets around the discrete amorphous regions completely and redefine the amorphous/crystalline interface.

Two-temperature principle for evaluating electrothermal performance of GaN HEMTs

Self-heating effects in Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) can adversely impact both device reliability and electrical performance. Despite this, a holistic understanding of the relationship among heat transport mechanisms, device reliability, and degradation of electrical performance has yet to be established. This Letter presents an in-depth analysis of self-heating effects in GaN HEMTs using technology computer-aided design and phonon Monte Carlo simulations. We examine the differential behaviors of the maximum channel temperature (Tmax) and the equivalent channel temperature (Teq) in response to non-Fourier heat spreading processes, highlighting their respective dependencies on bias conditions and phonon ballistic effects. Our study reveals that Tmax, a crucial metric for device reliability, is highly sensitive to both heat source-related and cross-plane ballistic effects, especially in the saturation regime. In contrast, Teq, which correlates with drain current degradation, shows minimal bias dependence and is predominantly influenced by the cross-plane ballistic effect. These findings emphasize the importance of optimizing device designs to mitigate both Tmax and Teq, with a particular focus on thermal designs influenced by the heat source size. This work contributes to a deeper understanding of self-heating phenomena in GaN HEMTs and provides valuable insights for enhancing device performance and reliability.

Robust reverse bias safe operating area and improved electrical performance in 3300 V non-proportionally scaled insulated gate bipolar transistors

Robustness under high-temperature clamped inductive turn-off has been compared systematically among 3300 V scaled insulated gate bipolar transistors (IGBTs) with scaling factor k from 1 to 10 by technology computer-aided design simulations. Degradation of the reverse bias safe operating area (RBSOA) has been observed in proportionally scaled IGBTs, especially at a high turn-off current density. A non-proportional scaling method has been proven to be able to restore the robustness degradation with RBSOA close to the original k = 1 case. Moreover, the method for adjusting R pf (P-floating connecting resistor) adds more flexibility to device design and also improves the overall electrical performance of non-proportionally scaled IGBTs. The adjustment of R pf has been found to have a minimal effect on the RBSOA.

Prediction of JTE breakdown performance in SiC PiN diode radiation detectors using TCAD augmented machine learning

The design of Junction Termination Extension (JTE) is an important step for meeting the reliability requirement of SiC PiN diode radiation detectors. For early evaluation, Technology Computer Aided Design (TCAD) software is often used to simulate the electronic property of detectors with different JTE parameters. But it is time consuming, which need 1 h or even longer for one case. Here, a TCAD augmented Machine Learning (ML) method based on the fully connected Neural Network (NN) algorithm is proposed to predict the breakdown performance quickly with different parameters of Spatial Modulation (SM) JTE. Utilized ∼5000 datum generated by TCAD simulation, the ML model could be established and achieve good prediction of breakdown voltage and location within a few seconds. As a semi-supervised learning model, its prediction accuracy of breakdown location is higher than 89.4 % and the determination coefficient R2 of breakdown voltage could be up to 0.97 compared with TCAD simulations. Moreover, this model could give the relationship curve of breakdown voltages and doping concentration, which is useful to choose an ideal structure with a wide implantation dose window. Based on this ML prediction model, the design cycle of SiC PiN diode radiation detectors could be reduced significantly.

Influence of charge traps on charge plasma-germanium double-gate TFET for RF/Analog & low-power switching applications

The device reliability on account of charge traps at the Al2O3/Ge interface is a main distress for the Ge-based Tunnel Field Effect Transistor (TFET). Here, the influence of Interface Trap Charges (ITC) on the charge plasma-based Ge-Double-Gate TFET (CP-Ge-DGTFET) and conventional Ge-DGTFET's DC, Analog/RF, and linearity characteristics have been inspected using technology-computer-aided-design (TCAD) simulations for the donor (positive) and acceptor (negative) ITC. The charge plasma concept is adopted to induce excess carrier concentration within the source region on the integration of optimum work function metal electrodes. To recognize the impact of ITC, several figures of merits have been investigated, such as transfer characteristics, electric field, transconductance, cut-off frequency, parasitic capacitance, and linearity performance parameters (VIP2, VIP3, IIP3, and IMD3). The CP-Ge-DGTFET device structure revealed superior performance and reliability in comparison to Ge-DGTFET, even under the influence of ITC at the Al2O3/Ge interface. Therefore, the CP-Ge-DGTFET device structure is a sturdy contender for Analog/RF and low-power switching applications.

Tailoring Subthreshold Swing in A-IGZO Thin-Film Transistors for Amoled Displays: Impact of Conversion Mechanism on Peald Deposition Sequences.

Amorphous IGZO (a-IGZO) thin-film transistors (TFTs) are standard backplane electronics to power active-matrix organic light-emitting diode (AMOLED) televisions due to their high carrier mobility and negligible low leakage characteristics. Despite their advantages, limitations in color depth arise from a steep subthreshold swing (SS) (≤ 0.1 V/decade), necessitating costly external compensation for IGZO transistors. For mid-size mobile applications such as OLED tablets and notebooks, it is important to ensure controllable SS value (≥ 0.3 V/decade). In this study, a conversion mechanism during plasma-enhanced atomic layer deposition (PEALD) is proposed as a feasible route to control the SS. When a pulse of a diethylzinc (DEZn) precursor is exposed to the M2 O3 (M = In or Ga) surface layer, partial conversion of the underlying M2 O3 to ZnO is predicted on the basis of density function theory calculations. Notably, significant distinctions between In-Ga-Zn (Case I) and In-Zn-Ga (Case II) films are observed: Case II exhibits a lower growth rate and larger Ga/In ratio. Case II TFTs with a-IGZO (subcycle ratio of In:Ga:Zn = 3:1:1) show reasonable SS values (313mV decade-1 ) and high mobility (µFE ) of 29.3cm2 Vs-1 (Case I: 84mV decade-1 and 33.4cm2 Vs-1 ). The rationale for Case II's reasonable SS values is discussed, attributing it to the plausible formation of In-Zn defects, supported by technology computer-aided design (TCAD) simulations.

Blue-light-enhanced avalanche photodiode with amulti-finger grating structure for fluorescence detection.

The responsiveness of the photodetectors is critical to the accuracy of the fluorescent fiber optical temperature sensor. However, the current gain and signal-to-noise ratio (SNR) of traditional photodiodes (PDs) is low, which makes it difficult to meet the high-precision detection requirements of the system. In response to the above problems, this paper achieves a novel, to the best of our knowledge, multi-finger grating (MFG) avalanche photodiode (APD). The device combines the polysilicon gate and the space charge region formed by P+/N-Well to detect photon signals. The conversion capability of the photodetector can be significantly enhanced by the MFG structure. The principle of the device is simulated and verified by technology-computer-aided design (TCAD). The standard grating APD (SG-APD), 2-finger grating APD (2FG-APD), 3-finger grating APD (3FG-APD), and 4-finger grating APD (4FG-APD) are fabricated based on 0.18µm CMOS process. The optoelectronic detection characteristics of these devices are analyzed by establishing an optoelectronic test platform. At 480nm, the responsivity of 2FG-APD, 3FG-APD, and 4FG-APD increases by 79.3%, 96.9%, and 70.2%, respectively, compared to SG-APD (4.021A/W). The test results indicate that 3FG-APD exhibits a strong photon response in the blue light range. The device has broad application prospects in the field of fluorescence detection.

Advances in the TCAD modelling of non-irradiated and irradiated Low-Gain Avalanche Diode sensors

The recently developed Low-Gain Avalanche Diode (LGAD) technology has gained growing interest within the high-energy physics (HEP) community, thanks to its capability of internal signal amplification that improves the particle detection. Since the next generation of HEP experiments will require tracking detectors able to efficiently operate in environments where expected fluences will exceed 1 × 1017 1 MeV n eq/cm2, the design of radiation-resistant particle detectors becomes of utmost importance. To this purpose, Technology Computer-Aided Design (TCAD) simulations are a relevant part of the current detector R&D, not only to support the sensor design and optimization, but also for a better understanding and modelling of radiation damage. In this contribution, the recent advances in the TCAD modelling of non-irradiated and irradiated LGAD sensors are presented, whose validation relies on the agreement between the simulated and experimental data — in terms of current-voltage (I-V), capacitance-voltage (C-V), and gain-voltage (G-V) characteristics, coming from devices manufactured by Hamamatsu Photonics (HPK), and accounting for different irradiation levels and temperatures.

Energy-Performance Assessment of Oscillatory Neural Networks Based on VO 2 Devices for Future Edge AI Computing.

Oscillatory neural network (ONN) is an emerging neuromorphic architecture composed of oscillators that implement neurons and are coupled by synapses. ONNs exhibit rich dynamics and associative properties, which can be used to solve problems in the analog domain according to the paradigm let physics compute. For example, compact oscillators made of VO 2 material are good candidates for building low-power ONN architectures dedicated to AI applications at the edge, like pattern recognition. However, little is known about the ONN scalability and its performance when implemented in hardware. Before deploying ONN, it is necessary to assess its computation time, energy consumption, performance, and accuracy for a given application. Here, we consider a VO 2 -oscillator as an ONN building block and perform circuit-level simulations to evaluate the ONN performances at the architecture level. Notably, we investigate how the ONN computation time, energy, and memory capacity scale with the number of oscillators. It appears that the ONN energy grows linearly when scaling up the network, making it suitable for large-scale integration at the edge. Furthermore, we investigate the design knobs for minimizing the ONN energy. Assisted by technology computer-aided design (TCAD) simulations, we report on scaling down the dimensions of VO 2 devices in crossbar (CB) geometry to decrease the oscillator voltage and energy. We benchmark ONN versus state-of-the-art architectures and observe that the ONN paradigm is a competitive energy-efficient solution for scaled VO 2 devices oscillating above 100 MHz. Finally, we present how ONN can efficiently detect edges in images captured on low-power edge devices and compare the results with Sobel and Canny edge detectors.