Technology Computer-aided Design Research Articles

Supported Pt Nanoclusters on Single-Layer MoS2 for the Detection of Cortisol: From Atomistic Scale to Device Modeling

The development of nonenzymatic sensors is a challenge which requires, on the one hand, careful design of the sensing materials with respect to the chosen analyte, and on the other hand, suitable device architectures. In this work, we propose single-layer molybdenum disulfide (MoS2) decorated with subnanometer Pt clusters as the sensing platform for the detection of cortisol. The aim is to assess the suitability of such a sensing platform for the development of wearable and portable cortisol sensors. For this study, we performed multiscale computer simulations at the materials level up to device scale. First, ab initio simulations within the framework of density functional theory (DFT) allowed us to gain insights into the interaction, at the atomic level, between the analyte (cortisol) and the sensing platform (MoS2/Pt). Then, by carrying out technology computer-aided design (TCAD) simulations, we were able to consider a device architecture and investigate its performance as cortisol sensor. Following our multiscale simulation strategy, we were able to assess the proposed field-effect transistor (FET) sensor, whose channel is made of Pt-decorated MoS2. The sensing mechanism relies on the chemiresistive response of the device to the adsorption of cortisol on the channel, which leads to a sizable charge transfer from the analyte to the substrate and, consequently, to the measurable shift in the gate voltage threshold of the FET. Our findings suggest that both the choice of the sensing materials and the proposed FET architecture are suitable for detecting cortisol by non-enzymatic means. In the best case scenario, we predict theoretical gate voltage shifts between 76 and 780 mV with respect to the cluster concentration and between 27 and 780 mV when varying the cluster occupancy by cortisol. We may expect our results to provide the necessary basis to develop highly sensitive nonenzymatic cortisol sensors based on 2D materials decorated with Pt nanoclusters.

Optimization of negative capacitance junctionless gate-all-around field-effect transistor using asymmetric non-local lateral Gaussian doping

Technology advancements directed towards Internet-of-Things (IoT) and wearable computing electronics applications are booming in low-power devices, which requires downscaling of power supply voltage without sacrificing the performance of the device. A negative capacitance junctionless gate-all-around field-effect transistor (NC-JL-GAAFET) is investigated using technology computer-aided design (TCAD) simulations to further suppress the short-channel effects and reduce power consumption. Lateral Gaussian doping (LGD), proposed for the NC-JL-GAAFET, is considered its main doping mode. An asymmetric structure with varying lengths of source/drain extension regions is introduced into non-local LGD NC-JL-GAAFET. The results reveal that the proposed device with a larger length ratio for drain extension region has a higher switching current ratio and lower subthreshold swing. Furthermore, the TCAD simulations validate that the electrical characteristics can be easily optimized by adjusting the ferroelectric (FE) layer thickness on the gate stack. Therefore, an asymmetric non-local LGD NC-JL-GAAFET provides a potential scaling solution for the next-generation low-power devices.

Correlating Structural and Electrical Characteristics of Threading Dislocations in GaN -on- Si Heterostructures and p - n Diodes by Multiple Microscopy Techniques

Structural and electrical properties of a- and a + c-type threading dislocations in metal-organic vapor-phase epitaxy-grown $\mathrm{Si}$-doped $\mathrm{Ga}\mathrm{N}$ (0001) are determined by combining multiple scanning probe microscopy approaches. The analysis examines the space-charge region (SCR) formed around dislocation cores and clarifies the role it plays in influencing the local recombination, the surface-potential characteristic, and even the conductivity. Direct evidence of the SCR is obtained from a differential capacitance (dC/dV) measurement at dislocation sites on the (0001) surface. Experimental dC/dV (V) measurement results supported by technology computer-aided design calculations of capacitance, accounting for the theoretical deep levels related to different atom-core structures of the identified dislocations, reveal quantitative differences in their respective trap densities. This study is extended to p-n $\mathrm{Ga}\mathrm{N}$ vertical diodes to analyze the doping distribution across active layers. Through a correlated cross-section investigation combining electron-channeling contrast-imaging microscopy, the underlying dislocations within the depth limited by the screening of their SCRs are found to severely impact the homogeneity of the cross-section dC/dV contrast in the low-doped n-type drift layer of the diodes. This raises serious concerns regarding any quantification efforts by differential capacitance measurements in $\mathrm{Ga}\mathrm{N}$ on $\mathrm{Si}$, where the dislocation density is in the order of ${10}^{9}\phantom{\rule{0.2em}{0ex}}{\mathrm{cm}}^{\ensuremath{-}2}$.

Random ferroelectric and dielectric phase distribution-induced device variation of negative capacitance field-effect transistors

Negative-capacitance field-effect transistors (NC-FETs) are significantly affected by their ferroelectric (FE)/dielectric (DE) phase configurations owing to the uncertainty of their crystalline phases. This study presents an analysis of random FE/DE grain distribution-induced variations from multiple perspectives using a seed random number generator in a technology computer-aided design (TCAD) simulation. The results obtained for the NC fully depleted silicon-on-insulator (NC-FDSOI) FETs indicate that device variations can be effectively reduced by increasing the probability of FE grains which improves the switching characteristics. Additionally, the FE distribution at the source presents a larger ON-state current (Ion), while the complete DE path from the source to the drain presents a larger OFF-state current (Ioff). The simulation results also demonstrate that reducing the lateral grain size reduces the device variations while improving the switching current ratio. Increasing the ferroelectric layer thickness of the NC-FDSOI FET can improve its switching performance; however, this also increases its variations. The random FE/DE distribution-induced variations can be reduced by adequately increasing the gate width through device scaling.

Modeling and Simulation Investigation of Ferroelectric-Based Electrostatic Doping for Tunnelling Field-Effect Transistor

In this paper, a novel ferroelectric-based electrostatic doping (Fe-ED) nanosheet tunneling field-effect transistor (TFET) is proposed and analyzed using technology computer-aided design (TCAD) Sentaurus simulation software. By inserting a ferroelectric film into the polarity gate, the electrons and holes are induced in an intrinsic silicon film to create the p-source and the n-drain regions, respectively. Device performance is largely independent of the chemical doping profile, potentially freeing it from issues related to abrupt junctions, dopant variability, and solid solubility. An improved ON-state current and ION/IOFF ratio have been demonstrated in a 3D-calibrated simulation, and the Fe-ED NSTFET's on-state current has increased significantly. According to our study, Fe-ED can be used in versatile reconfigurable nanoscale transistors as well as highly integrated circuits as an effective doping strategy.

Mechanical stress in a tapered channel hole of 3D NAND flash memory

Mechanical stress impact according to the taper angle in 3D vertical NAND flash memory (V-NAND) was investigated using technology computer-aided design simulation (TCAD). In the non-tapered V-NAND, the stress of the polysilicon channel is similar regardless of the number of layers and the position of the WL. On the other hand, in tapered V-NAND, as the taper angle decreases, the CD variation of the channel hole increases, and the compressive stress increases close to the lower WL. The compressive stress applied to the polysilicon channel produces a negative threshold voltage shift (ΔVth) due to conduction band lowering. In tapered V-NAND, the lower WL has a larger ΔVth than the upper WL, and a non-uniform Vth shift occurs. However, as the gate length of the tapered V-NAND is scaled down, the stress of the polysilicon channel is decreased, and the stress difference between the lower WL and upper WL is reduced; therefore, the non-uniform Vth shift is suppressed.

Prediction of SET on SRAM Based on WOA-BP Neural Network

<p>The incidence of high-energy particles into the semiconductor device would induce single event transients (SETs), which is a main threaten to MOS device. And the incidence distances and Linear Energy Transfers (LETs) have important effects on the SET current. A machine learning method based on Whale Optimization Algorithm-Back Propagation neural network (WOA-BPNN) model considering injection distances and LETs has been proposed to predict SET current in this paper. And this method could effectively reduce the simulation time from hours to seconds compared to device model. The current data that predicted by this method has been compared with the Technology Computer Aided Design (TCAD) simulation result which obtained in the background of the 40 nm process technology, the regression coefficient between the predicted value based on the proposed method and the TCAD simulation result was 99.76%, and the maximum integral relative error was 0.287% while the minimum integral relative error is 0.04%. Besides, the proposed method is also compared with PSO-BPNN (Particle Swarm Optimization, PSO) and GA-BPNN (Genetic Algorithm, GA), and the results demonstrated that the WOA-BPNN has prediction accuracy and timing saving advantages over the other two methods.</p> <p> </p>

Improvement in the Performance of P-Type Tunnel Oxide Passivated Contact Solar Cell With Selective Tunneling Junctions Underneath the Contacts on Front Side

Industrial silicon solar cells are now moving further from passivated emitter and rear contact (PERC) toward Tunnel Oxide Passivated contact (TOPCon) technology. The efficiency of the PERC solar cell is improved by TOPCon technology, in which the rear side is fully passivated by an oxide/poly-Si tunneling junction. The performance of a TOPCon solar cell may further be improved by the incorporation of selective tunneling junctions underneath the front contacts. Some fabrications have been reported on a similar structure for an n-type Si substrate but they have not achieved the expected results. Also, a detailed study has not been done yet. Using 3-D sentaurus technology computer aided design (TCAD) simulation software, a detailed analysis has been done on the modified structure through the optimization of the tunnel oxides, the interfaces, the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> poly-Si layer, the selective (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> -poly-Si) tunneling junctions underneath the front contacts, etc., which has not been done earlier. It is seen that a thick n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> poly-Si layer causes parasitic absorption of light, whereas a very thin poly-Si layer cannot provide sufficient field for tunneling of carriers. A thicker tunnel oxide produces a high series resistance, whereas a very thin tunnel oxide cannot restrict the minority carriers to reach to the contacts. Therefore, an optimization is required and the optimization is done based on a fabricated bifacial p-TOPCon solar cell reported in the literature with an efficiency of 21.2% and bulk lifetime of 200 μs. After performing all the modifications in the fabricated reference cell and optimizing different parameters, the efficiency is improved by 3.5% in absolute. The efficiency is further improved to 25.4% with the bulk lifetime of 1 ms.

A Quantum-Computing-Based Method for Solving Quantum Confinement Problem in Semiconductor

Technology computer-aided design (TCAD) of semiconductor devices relies on the numerical solution of differential equations in devices. Recent advances in quantum computing provide a new opportunity for TCAD simulations to be performed on a quantum computer. Based on a variational quantum algorithm, we develop a quantum-computing-based method to solve quantum confinement problems in semiconductor nanostructures. As the number of numerical discretization grid points for solving the Schrödinger equation increases, the number of qubits needed scales only logarithmically, ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${O}[\log(N)]$ </tex-math></inline-formula> . The method is applied to solve quantum confinement problems at all dimensions, which are related to confinement in a quantum well, semiconductor nanowire, and semiconductor quantum dot structures. The method can treat an anisotropic band structure and electrostatic potential in semiconductor nanostructures. We further show that the design of ansatz plays an important role in the performance of the method in terms of solution accuracy. The quantum-computing-based method can compute the energies and wave functions of both the ground and excited states with high accuracy.

Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current-voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.

Investigation of Si 1−X GeX source dual material stacked gate oxide pocket doped hetero-junction TFET for low power and RF applications

ABSTRACT In this paper, the applicability of dual material stacked gate-oxide-Pocket doped-hetero-junction tunnel field effect transistor (DMSGO-PD-HTFET) for low power switching and radio frequency (RF) applications is investigated. In this context, gate workfunction engineering, the stacked-gate-oxide (+) approach, and asymmetrical doping at the P+ source () and N+ drain regions are considered. N+ pocket at source-channel interface implements DMSGO-PD-HTFET and improves interband tunnelling rate. This research aims to improve the device’s switching ratio (/), average subthreshold swing (), and radio frequency (RF) performance. For this, the control gate work function, mole fraction (X), pocket thickness, and doping concentration are optimised. Next, the DC, analog/RF and linearity figure of merits of the proposed device is analysed and the performance is compared with conventional all-silicon dual-material stack gate oxide tunnel field effect transistor (DMSGO-TFET) and dual-material stacked gate oxide-hetero-junction tunnel field effect transistor (DMSGO-HTFET) with source using technology computer-aided design (TCAD) device simulator. Based on the comparative analysis, the optimised design with exhibits an average subthreshold swing () of 28.8 mV/decade, switching ratio (/) of 2 × 1012, cut-off frequency () of 216 (GHz), and other significant improvements in analog/RF and linearity performance parameters. The proposed device is therefore suitable for switching and RF applications.

Importance of the Buffer Layer Properties for the Performance of Perovskite/Silicon Tandem Solar Cells

The power conversion efficiency of two-terminal perovskite/silicon tandem solar cells recently surpassed 30%, demonstrating the great potential of this technology. The most common electron-selective contact is a stack of a buckminsterfullerene film, a tin oxide buffer layer, and a transparent conductive oxide. While research is conducted on improving the fullerene/perovskite interface and on removing the buffer layer, less focus is put on tuning the buffer layer properties. In this work, the interplay of the doping densities in the fullerene film and the tin oxide layer as well as the impact of the tin oxide electron affinity on the device performance is investigated using electrical numerical simulations (technology computer-aided design). The simulated power conversion efficiency increases with higher doping densities in the fullerene film and the tin oxide layer, while an increasing conduction band offset between the two materials leads to a decreasing device performance. The results of this work imply that the properties of the buffer layer directly influence the performance of the tandem solar cell. In addition, the importance of measuring various material and interface characteristics in order to derive an improved device understanding is stressed.

Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off.

Ultrahigh Rectification Ratio in an Asymmetric Metal/Semiconductor/Metal Nanoscale Tunneling Junction: Implications for High-Frequency Rectifiers

The ultrafast quantum-based electron-transport mechanism with a typical tunneling time of femtoseconds is appealing to fabricate high-frequency rectifier diode devices for applications such as solar energy harvesting, THz mixers, and infrared detectors. Here, we demonstrate an ultrahigh rectification of more than 104 and a large forward current density of 13.8 A/cm2 at −2 V in the structure of a metal/semiconductor/metal (MSM, Pt/ZnO/TiN) nanoscale tunneling junction. Technology computer-aided design (TCAD) simulations demonstrate that high rectification originates from the switching of the electron-transport mechanism between direct tunneling (DT) and Fowler–Nordheim tunneling (FNT) under positive and negative voltage biases, respectively. The quantum-based FNT mechanism gives very slight temperature dependence of currents in a wide temperature range of 100–400 K. This work opens an avenue for high-frequency rectifier diodes based on MSM nanoscale tunneling junctions.

Performance analysis of GaN‐FINFET for RFIC application with respect to different FinWidth's

AbstractGaN has become a prevailing semiconductor in case of power and RF applications. The higher ranking material parameters of GaN, like wider band‐gap, the higher breakdown electric field as well as higher electron velocity when compared to materials like Si, SiC, GaAs etc; allow GaN FINFET to reveal potential advantages such as high voltage and high frequency applications. In this work, a comprehensive study on RF and linearity analysis on Heterojunction‐free GaN layer FINFET through visual technology computer‐aided design (TCAD) device simulator is been illustrated. The influence of varying the Finwidth's of the device on numerous RF parameters like drain current, transconductance (gm), output conductance (gd), gate capacitances(Cgd and Cgs), cut‐off frequency (fT) are studied. And also, the impact of varying the Finwidth's of the device on the numerous linearity parameters like gm2, gm3, VIP3, IIP3, 1 dB compression point were also studied. It is been observed that the higher Finwidth value is more worthy for radio frequency integrated circuit (RFIC) applications.

A Theoretical Study of Negative Capacitance Field‐Effect Transistors Using Ferroelectrics Having First‐ and Second‐Order Phase Transitions

Herein, a theoretical study of negative capacitance field‐effect transistors (NCFETs) using ferroelectrics (FEs), having first‐ and second‐order phase transitions (FPT and SPT, respectively), applying the Landau–Devonshire (LD) theory, is presented. The expressions for the Landau parameters for FPT FEs are derived from the basic relations, and subsequently, these are used in the numerical models for the surface potential, gate charge, and drain current for NCFETs with FPT FEs, developed in this work. The results show an excellent match with those obtained from technology computer‐aided design (TCAD) simulations. Next, the Landau parameters and the numerical models for the charge and drain current for NCFETs with SPT FEs are developed, following a similar procedure, and then the results of these two structures are compared, along with those obtained from TCAD simulations, which shows an excellent match. The results bring out some interesting observations—notable among them is a higher Ion/Ioff ratio for FPT structures, as compared to that for SPT ones, caused by a reduction in the subthreshold current, with a marginal increase in the strong inversion current in the former. This feature, by itself, may make NCFETs with FPT FEs more suitable than those with SPT FEs for low‐power applications.

A Physics-Based Dynamic Compact Model of Ferroelectric Tunnel Junctions

In this letter, we proposed a dynamic compact model for metal-ferroelectric-semiconductor (MFS) ferroelectric tunnel junctions (FTJ) based on their device physics. The voltage control over dynamic polarizations and the semiconductor surface potentials is achieved for full-region operations, supporting complex FTJ state transitions. A unified and smooth current model across different regions was proposed by formulating tunneling transports in FTJ with complicated barrier shapes from the first-principle tunneling theory. The model was extensively verified with both experimental data and technology computer-aided design (TCAD) simulations, featuring accurate descriptions of multi-states, frequency dependent programming, and circuit simulations.

Novel Trench Inner-Spacer Scheme to Eliminate Parasitic Bottom Transistors in Silicon Nanosheet FETs

A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) is proposed based on fully calibrated Technology Computer-Aided Design (TCAD) simulation. Highly doped punch-through stopper (PTS) layers are generally used to suppress trpbt. Unfortunately, trpbt is still a fatal failure factor in electrical performance degradation when the source/drain (S/D) recess is overetched. Moreover, the proposed TIS scheme prevents the diffusion of S/D dopants toward the PTS region beneath the bottom gate, thereby inhibiting the formation of trpbt. Furthermore, the TIS-NSFETs exhibit excellent immunity to overetched S/D recess depth variations. Additionally, the thermal characteristics of the TIS scheme are compared to that of the bottom oxide (BOX) scheme forming dielectrics beneath the S/D epitaxies, one of the methods used to suppress trpbt. Lattice temperature caused by self-heating and thermal resistance in the TIS-NSFETs are much lower than that in the BOX-NSFETs for both n/p-type devices. The thermal advantage of TIS-NSFETs compared to BOX-NSFETs is confirmed in both DC and AC conditions, similar to an actual operating environment. Therefore, the proposed TIS scheme is highly recommended to eliminate the undesired trpbt without critical DC/AC degradation and to resolve poor heat dissipation problems in the BOX scheme simultaneously.

Optimization of 14 nm double gate Bi-GFET for lower leakage current

In recent years, breakthroughs in electronics technology have resulted in upgrades in the physical properties of the metal oxide semiconductor field effect transistor (MOSFET) toward smaller sizes and improvements in both quality and performance. Hence, the growth field effect transistor (GFET) is being promoted as one of the worthy contenders due to its superior material characteristics. A 14 nm horizontal double-gate bilayer graphene FET with a high-k/metal gate is proposed, which is composed of hafnium dioxide (HfO 2 ) and tungsten silicide (WSi x ) respectively . It is simulated and modelled using silvaco ATHENA and ATLAS technology computer-aided design (TCAD) tools, as well as the Taguchi L9 orthogonal array (OA). The threshold voltage (V TH ) adjustment implant dose, V TH adjustment implant energy, source/drain (S/D) implant dose, and S/D implant energy have all been investigated as process parameters. While the V TH adjustment tilt angle and the S/D implant tilt angle have both been investigated as noise factors. When compared to the initial findings before optimization, the I OFF has a value of 29.579 nA/µm, indicating a significant improvement. Findings from the optimization technique demonstrate excellent device performance with an I OFF of 28.564 nA/µm, which is closer to the international technology roadmap semiconductor (ITRS) 2013 target than before.

Bias Dependence of Non-Fourier Heat Spreading in GaN HEMTs

In this article, self-heating in gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is studied by combining the technology computer-aided design (TCAD) and phonon Monte Carlo (MC) simulations. The simulation results indicate that the bias-dependent heat generation in the channel can have a remarkable impact on the thermal spreading process and the phonon ballistic effects simultaneously. Based on the two-heat-source model, we propose a two-thermal-conductivity model to predict the device junction temperature with the consideration of bias-dependent phonon transport in the HEMT. The proposed model is easy to be coupled with the finite-element method (FEM)-based thermal analysis without the need for time-consuming multiscale electrothermal simulations.