TCAD Process Simulations Research Articles

Process-induced stress tuning to improve linearity performance in AlGaN/GaN HEMTs with SiNx passivation

Strain engineering has proven to be a useful technique for enhancing the performance of many modern-day transistors. Stress engineering can also have a non-trivial effect on the performance of GaN HEMTs, which are devices of choice for high-power, high-frequency microwave applications. Process-induced stress can have a significant effect on AlGaN/GaN HEMT electrical characteristics in addition to the growth-induced strain present due to lattice constant mismatch between device layers. Understanding the true impact of process-induced strain on AlGaN/GaN HEMT microwave performance is highly necessary. This is especially the case for nonlinearity effects which affect the high-frequency performance of the device. To the best of our knowledge, there is no systematic report on the effect of nitride passivation-induced stress on AlGaN/GaN HEMT device linearity. This work uses a systematic combination of TCAD process simulation and device simulation to quantify the effect of process-induced stress on the device’s linearity. This work demonstrates that nonlinearity effects can be minimized through proper tuning of stress by varying design-dependent parameters such as the nitride layer thickness. The effect of stress on highly important linearity parameters of the device like gm, gm2, gm3, VIP2, VIP3, IIP3 and IMD3 is investigated in detail. Comparing the compressive-stress device to the no-stress and tensile-stress devices, we conclude that the compressive stress device has a max gm2 value that is 61% and 71% higher respectively. The max gm3 for compressive stress is 0.13 A V−3 whereas those for no-stress and tensile stress are 0.067 A V−3 and 0.045 A V−3 respectively. However, the voltage-variations of VIP2, and the VIP3 parameters which are derived from these gm values shows that the compressive stress case can help achieve overall better device linearity by stress tuning. This work also studies how the effect of process-induced stress on device linearity varies with the crucial gate length parameter.

(Invited) Mechanical Stress Simulations for Advanced Logic Devices

Novel transistor concepts are continuously being investigated to scale beyond FinFETs and nanosheets. One such architecture is the Complementary FET (CFET), consisting of an NFET and a PFET fabricated on top of each other [1-4], offering increased device density thanks to its stacking. However, additional challenges arise, such as significantly complicated processing and higher complexity of the connections between devices. Another concern lies in the optimization of the device performance by incorporating mechanical channel strain: in particular for the top-channel device it is challenging to employ traditional stressors efficiently, as it is largely disconnected from the substrate underneath. The purpose of this study is to study whether a CFET technology, and especially its top-channel device can be properly stressed. To this end, a TCAD process simulation flow that mimics the relevant steps for stress modeling has been built using Sentaurus-Process [5].An example of a quarter-structure of the simulated CFET at the end of the simulation (after channel release) is shown in Fig. 1. The device has a gate length of 14nm, a fin-like silicon channel both for the top and bottom device (5nm width, 30nm height), and fully strained source/drain (S/D) epitaxial layers in the bottom and top devices. For the top (NFET) device, the source/drain epi does not fill up all available space but consists rather of a thin layer grown against the sidewalls of the device, as observed experimentally. Tungsten contacts are added to connect the devices, and a thin oxide layer is present in the source/drain regions to isolate the top from the bottom device.Fig. 2 shows the longitudinal channel stress in the channels for a varying composition of the top-channel S/D epi. A large compressive (i.e. negative) stress is generated in the bottom PFET channels, thanks to the strained Si0.5Ge0.5 bottom S/D epi. On the other hand, the channel stress in the top channel is much smaller and becomes more tensile (positive) for higher Ge% in the top S/D. This opposite trend from traditional S/D’s was reported for nanowires in [6] and can be explained by the fact that the top S/D does not fill up the available space, which leads also to a large reduction in absolute channel stress. Another observation from Fig. 2 is that the stress in the bottom channel is independent of the composition in the top S/D, indicating that the devices are mechanically decoupled. Fig. 3 plots the channel stress in the structure after various steps of the simulation, showing that a small channel stress is generated after S/D etch by the presence of the sacrificial layer (Si0.75Ge0.25) between the channels. Furthermore, dummy gate removal tends to increase the absolute channel stress. Finally, the bottom S/D epi growth does not affect the top-channel stress, again confirming the mechanical decoupling of both channels to first order. Fig. 4 shows how the channel stress is affected for an intrinsic tensile stress of 2GPa in the tungsten or oxide isolation between the devices. Tungsten is a rather ineffective stressor due to its high stiffness: less than 200MPa tensile top-channel stress is generated by a stressed tungsten in its S/D’s. For the bottom device, the effect is even smaller due to the increased distance between the bottom-tungsten and the channel. The oxide isolation proves to be a more efficient stressor for the top channel, leading to about 1GPa additional tensile stress which is concentrated at the bottom of the channel.The presentation will highlight the importance of other stress components besides longitudinal stress. Furthermore, whereas the results in Figs. 1-4 were obtained for fin-like (vertically elongated) devices, a CFET technology can also be built using nanosheet (horizontally elongated) channels. It will be shown that changing towards this type of channels leads to a significant change of the stressor effectiveness in CFET technologies. These insights will help us to continue improving the device performance in advanced transistor architectures like CFETs.

Atomic Diffusion Mechanism in BF2+ Implanted and Annealed n-Fz Si junction using Analytical Approach: Comparison with 2-D TCAD Process Simulation Result

Ion implantation controls the diffusion of the dopants inside the n-Fz Si bulk of the p+n Si microstrip detector. In order to understand about the diffusion mechanism of BF2 + molecules/dopants into the n-Fz Si bulk of Double Sided Silicon Strip Detector (back side) for the R3B Silicon Tracker, it is essential to know the precise information about the microscopic defect introduces inside the Si lattice of the detector for the next phase upgrade of the R3B experiment. The purpose of this paper is to present the atomic transport and electrical activation behavior of implanted BF2+ molecules/dopants at an energy of 80 KeV and a dose of 1015 ion/cm2 into the n-Fz Double Sided Silicon Strip Detector for the R3B Silicon Tracker after annealing at 400 °C - 1350 °C.The result shows the amorphous-crystalline interface position and recrystallization temperature using the results revealed from the 2-D TCAD process simulation of the Si microstrip detector.

TCAD-Based RF performance prediction and process optimization of 3D monolithically stacked complementary FET

Radio frequency devices based on the state-of-the-art gate-all-around (GAA) nanosheet CFET process suffer from extra parasitic capacitance due to the stacked architecture compared to planar or FinFET devices. In this study, we first calibrate the TCAD process simulation model to experimental data. Subsequently, the model is applied to the simulation of RF characteristics of CFET devices with similar design as our real devices. Subsequently, the influence of various design parameters of the CFET structure are investigated, with emphasis on high frequency characteristics. The optimal design for CFET-based RF device is determined, which resulted in and fT and fMax improvements by 3.74 times and 8.44 times, respectively.

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) can change with decreasing temperature from +20 °C to −180 °C. This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform. Firstly, when the temperature drops from +20 °C to −140 °C, the increased carrier mobility drives a slight increase in transient amplitude. However, as the temperature decreases further below −140 °C, the carrier freeze-out brings about an inflection point, which means the transient amplitude will decrease at cryogenic temperatures. To better understand this result, we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt’s new incomplete ionization model. The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional (2D) TCAD process simulation. In addition, we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions. The increase of the emitter–base junction’s barrier height at low temperatures could suppress this electron-injection phenomenon. We have also optimized the built-in voltage equations of a high current compact model (HICUM) by introducing the impact of incomplete ionization. The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures, and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

Extraction of roughness parameters at nanometer scale by Monte Carlo simulation of Critical Dimension Scanning Electron Microscopy

Uncertainties in the sub-nanometer range, the use of new materials, roughness, and the three-dimensional structures represent main challenges for the metrology of critical dimensions in nanostructures. In this paper, Monte Carlo modeling is used to investigate the correlation of the “true line edge roughness” of photoresist lines with the roughness rendered by Critical Dimension Scanning Electron Microscopy. Examples are presented, where realistic full-three dimensional photoresist structures in the nanometer range are generated by TCAD process simulation.

Boron implanted emitter for n-type silicon solar cell**Project supported by the National Natural Science Foundation of China (Grant Nos. 61275040, 60976046, and 61021003) and the National Basic Research Program of China (Grant No. 2012CB934200).

The effects of ion doses on the properties of boron implanted Si for n-type solar cell application were investigated with doses ranging from 5× 1014 cm− 2 to 2× 1015 cm− 2 and a subsequent two-step annealing process in a tube furnace. With the help of the TCAD process simulation tool, knowledge on diffusion kinetics of dopants and damage evolution was obtained by fitting SIMS measured boron profiles. Due to insufficient elimination of the residual damage, the implanted emitter was found to have a higher saturation current density (J0e) and a poorer crystallographic quality. Consistent with this observation, Voc, Jsc, and the efficiency of the all-implanted p+–n–n+ solar cells followed a decreasing trend with an increase of the implantation dose. The obtained maximum efficiency was 19.59% at a low dose of 5× 1014 cm− 2. The main efficiency loss under high doses came not only from increased recombination of carriers in the space charge region revealed by double-diode parameters of dark I–V curves, but also from the degraded minority carrier diffusion length in the emitter and base evidenced by IQE data. These experimental results indicated that clusters and dislocation loops had appeared at high implantation doses, which acted as effective recombination centers for photogenerated carriers.

Influence of Poisson equation boundary conditions and quantum corrections to carrier concentrations at material interfaces in TCAD process simulation

AbstractIn TCAD process simulation, the Poisson equation for electrostatic potential is usually solved in silicon and polysilicon regions, assuming a zero normal component of electric field (ZEF) boundary conditions (BCs) at material interfaces. This is correct for a free (or covered only with dielectric) flat surface of silicon, which is typical for 1D SIMS profile simulations. However, it is inaccurate in other important cases, in particular, under the gate of submicron MOS transistors, where more general BCs preserving the continuity of the flux of electric displacement should be applied. In a simulation, the choice of BCs changes the electrostatic potential near material interfaces and, thereby, impacts simulated dopant distributions and transistor characteristics. We introduced such general BCs in Sentaurus Process and applied them to the 2D simulation of CMOS transistors with polysilicon or metal gate. A noticeable (but moderate) increase of simulated threshold voltage in comparison to the ZEF BCs is demonstrated. In addition, the effect of carrier concentration reduction at silicon/dielectric interfaces due to quantum‐mechanical repulsion was introduced into a continuum process simulation using the modified local‐density approximation. This changes the dopant distributions in a nanometre thin layer in semiconductors at both sides of the gate oxide, resulting in a reduced concentration of the main dopant near the interface, which is most pronounced at high dopant concentrations. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Strain engineering of nanoscale Si MOS devices

The stress distribution in the Si channel regions of process-strained Si (PSS) MOSFETs with various widths and gate lengths was studied using TCAD process simulations. We show how these geometric effects can impact the achievable transistor performance gains. In this work, high-performance MOS devices have been achieved by stressors such as stressed SiN liner and S/D stressors such as SiGe alloy material and optimal geometric structure design. Strain engineering seems to be promising when considering mobility gain, carrier injection velocity, and ballistic efficiency of nanoscale MOS devices. This work helps the future MOS device design and demonstrates that strain engineering is important for future nanoscale device technology.

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

Angled implants for controlling gate–source/drain extension: A TCAD modeling study

TCAD process simulations are carried out on NMOS and PMOS to study the effect of high tilt in source/drain extension (SDE) implants and millisecond, non-melt laser anneals on junction depth and gate–SDE overlap. High tilt implants along with millisecond laser anneals are proposed as a solution for future device technology nodes (<65nm) to obtain very shallow (Xj<15nm), abrupt (<3nm/dec) junctions, with a degree of freedom to optimize gate overlap. TCAD modeling shows upon increasing the tilt angle from 0° to 30° the gate/extension overlap can increase from 2nm to over 10nm, without loss of shallow junction depth. Angled high tilt arsenic implants followed by laser anneals are also performed to study the junction depth and sheet resistance variations with tilt angle. Channeling issues at tilt angles are also analyzed and a solution based on Ge pre-amorphization is proposed to circumvent this problem. The TCAD results indicate that high tilt implant is a critical requirement on the low energy, high current implanter, and that such feature is important for controlling the gate–extension overlap with millisecond (“diffusion-light”) laser anneal technologies.