Process-induced stress tuning to improve linearity performance in AlGaN/GaN HEMTs with SiNx passivation

Abstract

Strain engineering has proven to be a useful technique for enhancing the performance of many modern-day transistors. Stress engineering can also have a non-trivial effect on the performance of GaN HEMTs, which are devices of choice for high-power, high-frequency microwave applications. Process-induced stress can have a significant effect on AlGaN/GaN HEMT electrical characteristics in addition to the growth-induced strain present due to lattice constant mismatch between device layers. Understanding the true impact of process-induced strain on AlGaN/GaN HEMT microwave performance is highly necessary. This is especially the case for nonlinearity effects which affect the high-frequency performance of the device. To the best of our knowledge, there is no systematic report on the effect of nitride passivation-induced stress on AlGaN/GaN HEMT device linearity. This work uses a systematic combination of TCAD process simulation and device simulation to quantify the effect of process-induced stress on the device’s linearity. This work demonstrates that nonlinearity effects can be minimized through proper tuning of stress by varying design-dependent parameters such as the nitride layer thickness. The effect of stress on highly important linearity parameters of the device like gm, gm2, gm3, VIP2, VIP3, IIP3 and IMD3 is investigated in detail. Comparing the compressive-stress device to the no-stress and tensile-stress devices, we conclude that the compressive stress device has a max gm2 value that is 61% and 71% higher respectively. The max gm3 for compressive stress is 0.13 A V−3 whereas those for no-stress and tensile stress are 0.067 A V−3 and 0.045 A V−3 respectively. However, the voltage-variations of VIP2, and the VIP3 parameters which are derived from these gm values shows that the compressive stress case can help achieve overall better device linearity by stress tuning. This work also studies how the effect of process-induced stress on device linearity varies with the crucial gate length parameter.