Angled implants for controlling gate–source/drain extension: A TCAD modeling study

Abstract

TCAD process simulations are carried out on NMOS and PMOS to study the effect of high tilt in source/drain extension (SDE) implants and millisecond, non-melt laser anneals on junction depth and gate–SDE overlap. High tilt implants along with millisecond laser anneals are proposed as a solution for future device technology nodes (<65nm) to obtain very shallow (Xj<15nm), abrupt (<3nm/dec) junctions, with a degree of freedom to optimize gate overlap. TCAD modeling shows upon increasing the tilt angle from 0° to 30° the gate/extension overlap can increase from 2nm to over 10nm, without loss of shallow junction depth. Angled high tilt arsenic implants followed by laser anneals are also performed to study the junction depth and sheet resistance variations with tilt angle. Channeling issues at tilt angles are also analyzed and a solution based on Ge pre-amorphization is proposed to circumvent this problem. The TCAD results indicate that high tilt implant is a critical requirement on the low energy, high current implanter, and that such feature is important for controlling the gate–extension overlap with millisecond (“diffusion-light”) laser anneal technologies.