Abstract
AbstractIn TCAD process simulation, the Poisson equation for electrostatic potential is usually solved in silicon and polysilicon regions, assuming a zero normal component of electric field (ZEF) boundary conditions (BCs) at material interfaces. This is correct for a free (or covered only with dielectric) flat surface of silicon, which is typical for 1D SIMS profile simulations. However, it is inaccurate in other important cases, in particular, under the gate of submicron MOS transistors, where more general BCs preserving the continuity of the flux of electric displacement should be applied. In a simulation, the choice of BCs changes the electrostatic potential near material interfaces and, thereby, impacts simulated dopant distributions and transistor characteristics. We introduced such general BCs in Sentaurus Process and applied them to the 2D simulation of CMOS transistors with polysilicon or metal gate. A noticeable (but moderate) increase of simulated threshold voltage in comparison to the ZEF BCs is demonstrated. In addition, the effect of carrier concentration reduction at silicon/dielectric interfaces due to quantum‐mechanical repulsion was introduced into a continuum process simulation using the modified local‐density approximation. This changes the dopant distributions in a nanometre thin layer in semiconductors at both sides of the gate oxide, resulting in a reduced concentration of the main dopant near the interface, which is most pronounced at high dopant concentrations. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)
Published Version
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