TCAD Device Simulations Research Articles

Thermal, mechanical, and electrical properties of Si-stacked nanosheet transistors using machine learning interatomic potentials

Thermal and mechanical properties play a key role in optimizing the performance of nanoelectronic devices. In this study, the lattice thermal conductivity (κL) and elastic constants of Si nanosheets at different sheet thicknesses were determined using recently developed machine learning interatomic potentials (MLIPs). A Si nanosheet with a minimum thickness of 10 atomic layers was used for model training to predict the properties of sheets with greater thicknesses. The training dataset was efficiently constructed using stochastic sampling of the potential energy surface (PES). Density functional theory (DFT) calculations were used to extract
the MLIP, which served as the basis for further analysis. The Moment Tensor Potential (MTP) method was used to obtain the MLIP in this study. The results showed that, at sub-6 nm sheet thickness, the thermal conductivity dropped to ∼ 7 % of its bulk value, whereas some stiffness tensor components dropped to ∼ 3 % of the bulk values. These findings contribute to the understanding of heat transport and mechanical behavior of ultrathin Si nanosheets, which is crucial for designing and optimizing nanoelectronic devices. The technological implications of the extracted parameters on nanosheet field-effect transistor (NS-FET) performance at advanced technology nodes were evaluated using TCAD device simulations.

Process-induced stress tuning to improve linearity performance in AlGaN/GaN HEMTs with SiNx passivation

Strain engineering has proven to be a useful technique for enhancing the performance of many modern-day transistors. Stress engineering can also have a non-trivial effect on the performance of GaN HEMTs, which are devices of choice for high-power, high-frequency microwave applications. Process-induced stress can have a significant effect on AlGaN/GaN HEMT electrical characteristics in addition to the growth-induced strain present due to lattice constant mismatch between device layers. Understanding the true impact of process-induced strain on AlGaN/GaN HEMT microwave performance is highly necessary. This is especially the case for nonlinearity effects which affect the high-frequency performance of the device. To the best of our knowledge, there is no systematic report on the effect of nitride passivation-induced stress on AlGaN/GaN HEMT device linearity. This work uses a systematic combination of TCAD process simulation and device simulation to quantify the effect of process-induced stress on the device’s linearity. This work demonstrates that nonlinearity effects can be minimized through proper tuning of stress by varying design-dependent parameters such as the nitride layer thickness. The effect of stress on highly important linearity parameters of the device like gm, gm2, gm3, VIP2, VIP3, IIP3 and IMD3 is investigated in detail. Comparing the compressive-stress device to the no-stress and tensile-stress devices, we conclude that the compressive stress device has a max gm2 value that is 61% and 71% higher respectively. The max gm3 for compressive stress is 0.13 A V−3 whereas those for no-stress and tensile stress are 0.067 A V−3 and 0.045 A V−3 respectively. However, the voltage-variations of VIP2, and the VIP3 parameters which are derived from these gm values shows that the compressive stress case can help achieve overall better device linearity by stress tuning. This work also studies how the effect of process-induced stress on device linearity varies with the crucial gate length parameter.

Research on single event effects and hardening design of LDMOS transistors

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm−2 mg−1). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.

Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor

This paper reports the characteristics study of a single phase full bridge power electronic inverter circuit with a new type of technology namely surrounded channel junctionless field effect transistor (SCJLFET) as a switch. The inverter circuit has been designed using mixed mode simulation platform of TCAD device simulator. The transient characteristics for various temperatures and work functions have been analysed. In the steady state analysis the output current and voltage variation with input voltage with various temperatures and work functions have been studied. The power factor variations with gate oxide thickness and dielectric constant of gate dielectric. The simulation and designing process along with pros and cons have been characterized. The SCJLFET would be one of the strongest participants for advanced power electronics technology as a switches, with various virtues of high-speed operation, low power consumption and low budget process integration. It has also been found that single phase full bridge inverter is giving best results when made using SCJLFET.

Ferroelectric Based Low Power MOSFET for DC/RF Applications: Machine Learning Assisted Statistical Variation Analysis

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. The utilization of gate side wall spacers aims to mitigate short-channel effects (SCEs), and improve overall device performance. Simulation results demonstrate enhanced performance metrics, including improved transconductance (80%), reduced gate leakage (95.4%), and enhanced cutoff frequency (25%), making this design a promising candidate for next-generation high-performance analog and RF applications. Additionally, a novel machine learning (ML)-assisted approach is proposed for investigating the spacer-based FE-MOSFET to reduce the computational cost of numerical TCAD device simulations with the help of conventional- artificial neural network (C-ANN). This method is reported for the first-time ML-based C-ANN for Fe-based low-power MOSFET, matches the similar accuracy of physics-based TCAD with the fastest learning rate and fastest computational speed (in 95–100 s). An ML-based prediction replacement for physics-based TCAD is developed to save around 8–10 h of runtime for each iteration. Because ML predictions can never be 100% accurate, it is essential to ensure approximately zero mean-square error in the final results.

Low‐frequency noise model development of MoS2 field effect transistor and its analysis with respect to different traps

AbstractIn this paper, an analytical drain current model of double gate MoS2 FET Transistor for low‐frequency noise (LFN) power spectral density is developed, and compared its response with the device simulation of the proposed device structure. The developed low‐frequency noise power spectral density (PSD) model is analyzed with respect to different Trap densities, Oxide thicknesses, and high K‐dielectric materials using the TCAD Device simulation tool. Low‐frequency noise is one of the most important noises in any device since it degrades the device's performance. So, in this paper, we used a unique charge‐control model for analyzing the low‐frequency noise by considering the mobility degradation, trapping, and de‐trapping effects caused by trap densities and device lattice structure. Usually, all the previous studies on drain currents with low frequency are based on fluctuations caused by mobility and carrier variations. In our paper, we even considered the charge density fluctuation to analyze the drain current equation. Using a Charge Control Model, we can compute the parameters like gate capacitance (Cgs, Cgd), channel length modulation, and body effect. While other LFN models like the DC model, small signal model, and hybrid model will focus mainly on the static characteristics of the device such as its DC current–voltage (I‐V) relationship, terminal resistances, and input/output conductance of the devices. All the analytical model results were calibrated with the device simulation and it is observed that both are matches each other. Further, it is observed that with an increase in Trap density, the low‐frequency noise increases and low‐frequency noise is dominant at lower frequencies only (1–10 Hz), and after this frequency range the thermal noise will be the dominant noise factor.

TCAD Device Simulation With Graph Neural Network

TCAD Device Simulation With Graph Neural Network

Proposal and Numerical Analysis of Organic/Sb2Se3 All-Thin-Film Tandem Solar Cell.

The low bandgap antimony selenide (Sb2Se3) and wide bandgap organic solar cell (OSC) can be considered suitable bottom and top subcells for use in tandem solar cells. Some properties of these complementary candidates are their non-toxicity and cost-affordability. In this current simulation study, a two-terminal organic/Sb2Se3 thin-film tandem is proposed and designed through TCAD device simulations. To validate the device simulator platform, two solar cells were selected for tandem design, and their experimental data were chosen for calibrating the models and parameters utilized in the simulations. The initial OSC has an active blend layer, whose optical bandgap is 1.72 eV, while the initial Sb2Se3 cell has a bandgap energy of 1.23 eV. The structures of the initial standalone top and bottom cells are ITO/PEDOT:PSS/DR3TSBDT:PC71BM/PFN/Al, and FTO/CdS/Sb2Se3/Spiro-OMeTAD/Au, while the recorded efficiencies of these individual cells are about 9.45% and 7.89%, respectively. The selected OSC employs polymer-based carrier transport layers, specifically PEDOT:PSS, an inherently conductive polymer, as an HTL, and PFN, a semiconducting polymer, as an ETL. The simulation is performed on the connected initial cells for two cases. The first case is for inverted (p-i-n)/(p-i-n) cells and the second is for the conventional (n-i-p)/(n-i-p) configuration. Both tandems are investigated in terms of the most important layer materials and parameters. After designing the current matching condition, the tandem PCEs are boosted to 21.52% and 19.14% for the inverted and conventional tandem cells, respectively. All TCAD device simulations are made by employing the Atlas device simulator given an illumination of AM1.5G (100 mW/cm2). This present study can offer design principles and valuable suggestions for eco-friendly solar cells made entirely of thin films, which can achieve flexibility for prospective use in wearable electronics.

TCAD Device Simulation of All-Polymer Solar Cells for Indoor Applications: Potential for Tandem vs. Single Junction Cells.

The utilization of indoor photovoltaics makes it feasible to harvest energy from artificial light sources. Although single-junction indoor photovoltaics have demonstrated exceptional efficacy when using LED lighting, there is still a need for more comprehensive testing of tandem structures. Herein, the first systematic TCAD simulation study on the potential for tandem all-polymer solar cells (all-PSCs) for indoor applications is provided. The presented all-PSCs are based on experimental work in which the top wide bandgap subcell comprises a polymer blend PM7:PIDT, while the bottom narrow bandgap subcell has a polymer blend PM6:PY-IT. Standalone and tandem cells are simulated under AM1.5G solar radiation, and the simulation results are compared with measurements to calibrate the physical models and material parameters revealing PCE values of 10.11%, 16.50%, and 17.58% for the front, rear, and tandem cells, respectively. Next, we assessed the performance characteristics of the three cells under a white LED environment for different color temperatures and light intensities. The results showed a superior performance of the front cell, while a deterioration in the performance was observed for the tandem cell, reflecting in a lower PCE of 16.22% at a color temperature of 2900 K. Thus, an optimized tandem for outdoor applications was not suitable for indoor conditions. In order to alleviate this issue, we propose designing the tandem for indoor lightening by an appropriate choice of thicknesses of the top and bottom absorber layers in order to achieve the current matching point. Reducing the top absorber thickness while slightly increasing the bottom thickness resulted in a higher PCE of 27.80% at 2900 K.

Improved performance HEMT device with backup bulk for LNA application

This study proposes a 30 nm gate length double-gate InAlN/GaN on a 4H-SiC substrate high-electron-mobility transistor. Different electrical characteristics such as DC, AC, capacity and noise analysis were performed through TCAD device simulations. The proposed device exhibited a maximum drain current of 2.15 A mm−1, a transconductance of 1308 mS/mm, (350/610) GHz of FT/FMAX and a maximum noise figure of NFMax = 9.5 dB at 1 THz. Thus, LNA-HEMT has been designed considering the main characteristics of power with a new structure, in terms of temperature and low noise figure effect. Adopting the backup bulk in the optimization procedure, the proposed device obtained an outstanding performance with appropriate low power consumption for the GEO satellite application.

Experimental investigation of time dependent dielectric breakdown and failure mechanism for Hf0.5Zr0.5O2 ferroelectric field effect transistors

The experimental investigation of the time dependent dielectric breakdown (TDDB) was performed to study the dielectric breakdown mechanisms for Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs) with the SiO2 interfacial layer (IL). Constant voltage stress method combined with the TCAD device simulation was used to study the breakdown mechanism of the TaN/HZO/SiO2/Si gate stack. Due to the much higher electric field in the IL, the breakdown of the SiO2 IL is the major reason for the breakdown of the gate stack. In addition, it is found that the IL breakdown will speed up the disappearance of the memory window (MW), leading to the malfunction of the FeFET as a storage device. Finally, the Weibull distributions of time-to-breakdown (TBD) and charge-to-breakdown (QBD) were characterized, revealing decent TDDB performance of the FeFETs. Careful design of IL thickness is necessary to balance the tradeoff between the device performance and the reliability lifetime of HZO FeFETs.

Simulation study on the influence of metal contact and MOS interface trap states on the electrical characteristics of SiC IGBT

A 13 kV class n-channel 4H–SiC trench gate insulated gate bipolar transistor (IGBT) structure is designed based on Silvaco TCAD device simulator tool. The influence of metal/SiC and SiC MOS interface trap states on the static and dynamic characteristics of SiC IGBT devices are systematically studied. It is found that the electrical properties of SiC IGBTs are insensitive to the donor or acceptor traps at the interface of metal/SiC and the donor traps at the SiC/SiO2 interface. However, the acceptor traps at the SiC/SiO2 interface affect the electrical properties of SiC IGBTs greatly. When the acceptor trap density at the SiC/SiO2 interface (Dita) is up to the level of 1012 cm−2·eV−1, the turn-on voltage drop (VCEON) is increased gradually with the augmentation of Dita. The breakdown voltage (VBR) of the device is increased slightly. Further study of the device’s turn-off characteristics shows that the turn-off loss (EOFF) is decreased with the increase in Dita but a large tail current is formed. The mechanism may be that when the electrons are injected from the N+ source region into the N− drift region, the SiC/SiO2 interfacial acceptor traps at the side wall of trench gate capture a large number of electrons. As a result, the minority carrier concentration is decreased, and the conductance modulation effect on the N− drift region is weakened.

Design and Investigation of a Single Gate Heterostructure Junctionless Tunnel FET for the Gas Detection

In this paper, a single gate junctionless heterostructure TFET gas sensor (SiGe-SG-JLTFET) is presented, and its effectiveness is examined. The high-k gate dielectric (HfO2) and low bandgap alloy prove to be a great combination to boost the drain current. The leakage current is controlled by the presence of a silicon body in the channel and drain. We have considered a Palladium metal with a suitable work-function in the gate catalyst for better sensitivity purposes. The sensor modulates the flat band voltage and Capacitance-Voltage characteristics with the adsorption of gas atoms at the Palladium/HfO2 and Palladium surfaces. Consequently, the ON-state current is affected, which is treated as a sensing measure. The gas sensor’s electrostatic analysis is investigated in terms of I-V characteristics, current components, band energy for both ON- and leakage conditions, maximum electric field, BTBT rate, and carrier concentrations. Similarly, the sensitivity analysis consists of drain current sensitivity (SID), current ratio sensitivity (Sratio), and average SS sensitivity (SSS). The investigation has been carried out with the change in gas pressure in terms of work-function, temperature (0K), and interface trap charges (ITC) using a TCAD device simulator. The proposed gas sensor exhibits a (SID)max of 2.41 × 106 and Sratio of 3.89 × 104 with higher pressure concentration at room temperature respectively.

Analytical and Numerical Investigation of Nanowire Transistor X-ray Detector

Recently, nanowire detectors have been attracting increasing interest thanks to their advantages of high resolution and gain. The potential of using nanowire detectors is investigated in this work by developing a physically based model for Indium Phosphide (InP) phototransistor as well as by performing TCAD simulations. The model is based on solving the basic semiconductor equations for bipolar transistors and considering the effects of charge distribution on the bulk and on the surface. The developed model also takes into consideration the impact of surface traps, which are induced by photogenerated carriers situated at the surface of the nanowire. Further, photogating phenomena and photodoping are also included. Moreover, displacement damage (DD) is also investigated; an issue arises when the detector is exposed to repeated doses. The presented analytical model can predict the current produced from the incident X-ray beam at various energies. The calculation of the gain of the presented nanowire carefully considers the different governing effects at several values of energies as well as biasing voltage and doping. The proposed model is built in MATLAB, and the validity check of the model results is achieved using SILVACO TCAD device simulation. Comparisons between the proposed model results and SILVACO TCAD device simulation are provided and show good agreement.

RF and Linearity Analysis of Heterojunction-free Ga2O3 FINFET with Respect to Different Fin Widths and Temperatures

In this paper we have proposed a Heterojunction free Ga2O3 FinFET, and the different electrical characteristics have been analysed. Fin width is one of the most important parameters for the device performance, hence all the electrical charaterstics have been analysed for different fin widths. Temperature is one of the most important considerations for high power applications and hence electrical characteristics have been analysed by varying temperature also. Here, in the work done an exhaustive study on the RF and Linearity analysis on Heterojunction-free Ga2O3 layer FINFET using TCAD device simulator is demonstrated. The impact when varying the widths of fin along with the temperature variation for the device on various RF parameters like Drain current, gm (Transconductance), gd (output Conductance), Cgs and Cgd (gate capacitances), fT (cut-off frequency) are studied. The same has been performed even to calculate different linearity parameters such as gm2, gm3, VIP3, IIP3, IMD3, 1db compression point. It’s observed that to have high value for fin width and to have lower temperature value is much worthier for RFIC applications. In order to exhibit the superiority of the Ga2O3 FINFET it has been compared with the SOI FINFET.

Normally-Off β-(AlxGa1-x)2O3/Ga2O3 Modulation-Doped Field-Effect Transistors With p-GaN Gate: Proposal and Investigation

A novel <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\beta $ </tex-math></inline-formula> -(AlxGa1-x)2O3/gallium oxide (Ga2O3) modulation-doped field-effect transistor (MODFET) with p-GaN gate is proposed and investigated for the first time. TCAD device simulator calibrated with experimental results is used to develop the physical insight of device operation and to evaluate the proposed device’s performance. Besides normally- OFF operation, the proposed MODFET also shows a higher driving capability and lower ON-resistance compared to conventional Ga2O3-MODFETs of similar device dimensions. The effect of individual device parameters on the electrical characteristics of the proposed device is also investigated in detail. Besides, an analytical model is formulated to estimate the threshold voltage of these normally- OFF devices. This model is rigorously validated with numerical results for a wide range of device parameters.

Study of depth-dependent charge collection profiles in irradiated pad diodes

In this work, charge collection profiles of non-irradiated and irradiated 150µm thick p-type pad diodes were measured using a 5.2GeV electron beam traversing the diode parallel to the readout electrode. Four diodes were irradiated to 1MeV neutron equivalent fluences of 2, 4, 8, and 12 × 1015cm−2 with 23MeV protons. The Charge Collection Efficiency profiles as a function of depth are extracted by unfolding the data. The results of the measurements are compared to the TCAD device simulation using three radiation damage models from literature which were tuned to different irradiation types and fluences.

Analysis of Bulk and Surface Radiation Damage in n+ in p SFz Si Micro Strip Detectors for the Future High Luminosity Collider Experiments: TCAD Simulation and Measurements

Within the framework of CERN RD50 collaboration, several radiation damage models for n/p-SFz, n-MCz Si have been explored for the better understanding of the experimental results in radiation damage analysis of the irradiated Si detectors. In the present paper, the important review on the microscopic radiation damage model for the p-type SFz Si detector combining the surface and radiation damage effects that can be used to simulate radiation damages effects in the heavily irradiated detectors for the good comparison of the experimental data and simulation result. The surface radiation damage models were extracted from the experimental measurements on the p-MOS capacitor and Gate-Controlled Diodes irradiated by Gamma or X-ray radiations in the range of 10 to 500 Mrad (Si). Whereas, the bulk damage model microscopic parameter was extracted from the experimental (TSC, DLTS) measurements on the n in p-SFz Si microstrip detector. The radiation damage (surface and bulk) models can be fed into the commercial Synopsys TCAD device simulator program for the designing and optimization of the detector, which can be used in the very harsh radiation environment of the HL-LHC, or FCC experiment. The objective of this analysis was to verify the experimental results using the new microscopic radiation damage models on the p-SFz Si for the radiation damage analysis of p- SFz Si detectors irradiated by proton, neutron or mixed at very high fluences. The results were verified by comparison of the experimental data with TCAD simulation.

ALD-grown two-dimensional TiSx metal contacts for MoS2 field-effect transistors.

Metal contacts to MoS2 field-effect transistors (FETs) play a determinant role in the device electrical characteristics and need to be chosen carefully. Because of the Schottky barrier (SB) and the Fermi level pinning (FLP) effects that occur at the contact/MoS2 interface, MoS2 FETs often suffer from high contact resistance (Rc). One way to overcome this issue is to replace the conventional 3D bulk metal contacts with 2D counterparts. Herein, we investigate 2D metallic TiSx (x ∼ 1.8) as top contacts for MoS2 FETs. We employ atomic layer deposition (ALD) for the synthesis of both the MoS2 channels as well as the TiSx contacts and assess the electrical performance of the fabricated devices. Various thicknesses of TiSx are grown on MoS2, and the resultant devices are electrically compared to the ones with the conventional Ti metal contacts. Our findings show that the replacement of 5 nm Ti bulk contacts with only ∼1.2 nm of 2D TiSx is beneficial in improving the overall device metrics. With such ultrathin TiSx contacts, the ON-state current (ION) triples and increases to ∼35 μA μm-1. Rc also reduces by a factor of four and reaches ∼5 MΩ μm. Such performance enhancements were observed despite the SB formed at the TiSx/MoS2 interface is believed to be higher than the SB formed at the Ti/MoS2 interface. These device metric improvements could therefore be mainly associated with an increased level of electrostatic doping in MoS2, as a result of using 2D TiSx for contacting the 2D MoS2. Our findings are also well supported by TCAD device simulations.

Analysis of Drain-Induced Barrier Lowering in InGaZnO Thin-Film Transistors

Characterization of short-channel amorphous indium gallium zinc oxide (InGaZnO) (a-IGZO) thin-film transistors (TFTs) has been a crucial issue to realize higher resolution display and heterogeneous integration with complementary metal–oxide–semiconductor (CMOS) technology. In this work, the drain-induced barrier lowering (DIBL) of the a-IGZO TFT was investigated with the variations in oxygen content in the IGZO layer. In order to accurately investigate the effect of the drain voltage on the channel potential, it is necessary to analyze the energy band diagram based on the dopant profile of the channel region. A new method for extracting the channel dopant profile through a simple <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> measurement of the a-TFT sample was proposed. We performed TCAD device simulation based on the extracted density of states and dopant profile of IGZO layer and confirm good agreement with the measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics of a-IGZO TFTs with various oxygen contents. The effective channel length was found to be short with decreasing the oxygen content in the IGZO channel layer. The DIBL effect becomes more severe as the oxygen content decreases. Our methodology, which was successfully verified in this work, can be utilized for the analysis of short-channel effects including DIBL for the scaled a-IGZO TFTs.