TCAD Device Simulations Research Articles

Modeling of dual material surrounding split gate junctionless transistor as biosensor

In this paper an analytical model of dual material surrounding split gate junctionless transistor for application as a biosensor is introduced. The simulation results show fair compatibility with the analytical models developed for the channel center potential and threshold voltage at channel length of 45 nm and 20 nm. For the detection of the bio-molecules, concept of dielectric modulation has been used. The model shows a satisfactory value of sensitivity in the range of 0–0.27 and 0–0.8 for relative permittivity of biomolecules varying from 1 to 9 at channel length of 45 nm and 20 nm respectively, thus making it an attractive option for use as biosensor. This model has been demonstrated with the aid of TCAD device simulations. • Present work includes modelling of dual material surrounding split gate junction less transistor for bio-sensing application. • The model for channel centre potential and threshold voltage has been developed. • Sensitivity is defined in terms of change in threshold voltage of the device. • Decent sensitivity in the range of 0–0.27 and 0–0.8 for 45 nm and 20 nm technology respectively is observed for relative permittivity varying from 1–9.

Ion-Sensitive Gated Bipolar Transistor

In this article, we study the ion-sensitive gated bipolar transistor (ISBiT) by forward biasing the source-body diode of the ion-sensitive field-effect transistor (ISFET). Based on theory, extensive TCAD device simulations, and experiments, it is shown that the ISBiT operates at lower gate-voltages with a higher transconductance ( ${g}_{m}$ ) than the ISFET both in subthreshold and near-threshold modes. In addition, overall maximum $g_{m}$ ’s have been obtained for the former when operating in saturation mode. However, in the linear superthreshold operation mode, the ISBiT shows lower $g_{m}$ ’s because of the field-induced mobility reduction. The same trends have been obtained for the pH-sensitivity expressed as $\partial {I}_{\text {D}}/\partial {\text {pH}}$ , since it is linearly dependent on the ${g}_{m}$ , as predicted by the theory. Basically, the ISBiT offers more tunability, hence, freedom in the sensor system.

Short Circuit Capability and Short Circuit Induced $V_{\mathrm{TH}}$ Instability of a 1.2-kV SiC Power MOSFET

The withstand capability and threshold voltage ( $V_{\mathrm {TH}}$ ) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer $I$ – $V$ characteristics and gate-to-source leakage current ( $I_{\mathrm {GSS}}$ ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations ( $t_{p}$ ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be $\sim 3.3~\mu \text{s}$ . $V_{\mathrm {TH}}$ instability under repetitive SC tests prior to the device failure is characterized. A bidirectional $V_{\mathrm {TH}}$ shift behavior, i.e., negative shift at shorter $t_{p}$ and positive shift at longer $t_{p}$ , was revealed. The $V_{\mathrm {TH}}$ shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex $V_{\mathrm {TH}}$ shift behavior are explained in a unified framework by taking into account the junction temperature ( $T_{j}$ ) increase with longer $t_{p}$ . TCAD device simulation is used to help analyze the mechanisms.

An Analytical Model of Single-Event Transients in Double-Gate MOSFET for Circuit Simulation

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter.

Machine Learning Approach for Predicting the Effect of Statistical Variability in Si Junctionless Nanowire Transistors

This letter investigates the possibility to replace numerical TCAD device simulations with a multi-layer neural network (NN). We explore if it is possible to train the NN with the required accuracy in order to predict device characteristics of thousands of transistors without executing TCAD simulations. Here, in order to answer this question, we present a hierarchical multi-scale simulation study of a silicon junctionless nanowire field-effect transistor (JL-NWT) with a gate length of 150 nm and diameter of an Si channel of 8 nm. All device simulations are based on the drift-diffusion (DD) formalism with activated density gradient (DG) quantum corrections. For the purpose of this letter, we perform statistical numerical experiments of a set of 1380 automictically different JL-NWTs. Each device has a unique random distribution of discrete dopants (RDD) within the silicon body. From those statistical simulations, we extract important figures of merit (FoM) such as OFF-current (IOFF) and ON-current (ION), subthreshold slope (SS), and voltage threshold (VTH). Based on those statistical simulations, we train a multi-layer NN and we compare the obtained results with a general linear model (GLM). This shows the potential of using NN in the field of device modeling and simulation with a potential application to significantly reduce the computational cost.

An explicit method to extract fitting parameters in lumped-parameter equivalent circuit model of industrial solar cells

An explicit parameter-extraction method is proposed to estimate the values of fitting parameters in lumped-parameter equivalent circuit model of industrial solar cells. The explicit method is based on polynomial fitting curves on Matlab platform, TCAD device simulation results of Silvaco Atlas, and experimental data of silicon-based solar cells’ current-voltage characteristics. Such an explicit parameter-extraction method can be directly applied into the analytical solutions to one-diode lumped-parameter equivalent circuit model to complete the simulations for electrostatic properties of solar cells. First, the current-voltage characteristics of industrial silicon-based solar cells are also derived analytically as the previous works completed by other researchers and the four key factors especially for the maximum power formula are solved through the effective diode approach. Second, polynomial curve is used to fit current-voltage characteristics from simulation and experiment results of solar cells under illumination. Third, the polynomial fitting result, the short circuit current, and the open circuit voltage are used to extract explicitly all of five parameters included in the one-diode lumped-parameter equivalent circuit model for industrial solar cells. Finally, the extracted fitting parameters are substituted into the analytical solution to current-voltage characteristics and the obtained current-voltage characteristics are compared with device simulation results from Silvaco Atlas and experimental data from silicon-based solar cells. As a result, such an explicit extraction procedure could be regarded as a fast and accurate method to estimate model parameters in industrial solar cells, which is important for not only photoelectric device simulations but also process analysis.

Dynamics Analysis of Single Shockley Stacking Fault Expansion in 4H-SiC P-i-N Diode Based on Free Energy

Expansion of single Shockley stacking faults (SSFs) during forward current operation is an important issue, because it decreases the reliability of 4H-SiC bipolar devices. In this paper, we propose a method for analyzing SSF dynamics based on free energy under current conduction, temperature, and resolved shear stress conditions. The driving force for dislocation dissociation reactions and formation of SSFs is incorporated into the free energy function, including chemical potential, stacking fault energy, crystallographic energy, gradient energy and elastic strain energy. The net energy gain of the chemical potential was calculated as a function of temperature and current conduction through use of the a TCAD device simulator based on the Boltzmann equation, Poisson equation and the current continuity equation concerning electron and hole distributions with self-consistency. It was confirmed that SSF dynamics can be simulated by the proposed method. It was also found that SSF formation can be attributed to quantum well variation in which electrons in n-type 4H–SiC enter SSF-induced quantum well states to lower the energy of the dislocation system.

Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor With Substrate Bias-Induced Effects

In this paper, a surface potential-based drain current model is developed to explore the static and quasi-static performance of substrate-biased tri-gate junctionless field-effect-transistors (TGJLFETs). The effects of substrate bias voltage on surface potential, charge density, and drain current are analyzed. The 2-D Poisson’s equation is solved to obtain front and back surface potentials incorporating the effect of substrate bias voltage for a long-channel TGJLFET. The front and back surface potentials are subsequently utilized to obtain total conduction charge density and drain current. Further, short-channel and quantum mechanical corrections are incorporated in the model to use it for scaled devices. Moreover, the terminal charges calculated using Ward–Dutton’s charge partitioning scheme are utilized to model the transcapacitances and quasi-static drain current for TGJLFET. Further, an equivalent large-signal transient model of the device is implemented in SPICE using Verilog-A, and the transient behavior of inverter and ring oscillator circuits are simulated and studied. The models are validated using a 3-D Visual TCAD device simulator from Cogenda Pvt. Ltd.

Impact of different localized trap charge profiles on the short channel double gate junctionless nanowire transistor based inverter and Ring Oscillator circuit

In this paper, the reliability issues due to localized charges on Double Gate Junctionless Nanowire Transistor (DG-JNT) based circuits are investigated. The localized/fixed charges come into existence at the interface of substrate and oxide in the device during the manufacturing due to radiation, stress, process and hot carriers damage which significantly alters various characteristics of the device. The damage due to different profiles of localized charges on several parameters of DG-JNT based P-MOSFET is analyzed. Also, for analog circuit application, this work explicitly reports the comprehensive analysis of localized charge profiles on DG- JNT based CMOS inverter and three Stage Ring Oscillator circuit at 20 nm Gate length. The simulated results are obtained using Silvaco Atlas, TCAD device simulator.

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture.

Impact of WFV on electrical parameters due to high-k/metal gate in SiGe channel tunnel FET

This paper presented findings on statistical impact of mole fraction (x) on threshold voltage, on current, and off current in high-k/metal gate SiGe channel Tunnel FET (TFET) due to work function variability (WFV) of the metal gate. The analysis was carried out for varying mole fractions (x), average grain sizes, and device dimensions, using 3D TCAD device simulator. Our investigation showed that the fluctuation in threshold voltage (σVT) is noticeably affected by x, and grain sizes of metal gate. However, for large grain size, there is insignificant variation in σVT with an increase in x. Moreover, the distribution of threshold voltage is close to Gaussian for small grain size and bimodal for large grain size. The variation in on current (σIon) increases by negligible amount whereas off current fluctuation (σIoff) decreases significantly with increase in x. Further, the fluctuation in σVT with channel width is significant, but negligible with gate length.

Electrostatically doped drain junctionless transistor for low-power applications

Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD–JLT is an n+–n+–i–n+ structure that widens the tunnel barrier at the gate–drain interface in the OFF-state (VGS = 0 V, VDS = 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD–JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD–JLTs of gate length 20 nm offer a significant reduction in IOFF (~ 4 orders) while substantially improving ION/IOFF ratio (~ 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled-down structure, EDD–JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (GmRo), transconductance generation factor (Gm/ID), output conductance (GD), channel length modulation, and drain-induced barrier lowering of EDD–JLTs are also significantly improved as compared to conventional JLTs.

A low-leakage and high-writable SRAM cell with back-gate biasing in FinFET technology

This paper presents a novel low-leakage and high-writable 8T SRAM cell based on FinFET technology. This cell reduces leakage current and consequently leakage power by dynamically adjusting the back gate of the stacked independent-gate FinFET devices. Furthermore, these stacked transistors increase the write static noise margin of the proposed cell due to their role in reducing the strength of the pull-down network of the cross-coupled inverters. The characteristics of this cell are evaluated by device/circuit level simulations using Sentaurus device TCAD device simulator at different supply voltages and in the presence of process variations. The results indicate that the proposed SRAM cell reduces the static power by 37% and 56%, respectively, while providing comparable and even higher static noise margins, as compared to the 6T and 8T FinFET-based SRAM cells.

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.

Mathematical Modeling of Junctionless Triple Material Double Gate MOSFET for Low Power Applications

This paper describes the analytical modeling and simulation of Triple Material Double Gate Metal Oxide Semiconductor Field Effect Transistor (TMDG MOSFET) with no junctions. Three kind of gate materials with different work function values over the channel helps to improve the ON current and to form a barrier in the channel helps to reduce OFF current. It has been found from the obtained results that the OFF current or leakage current of the device is exactly low (IOFF =10-11 A) which is fit for low power applications. Also, the extracted value of ION current (10-3 A) has proved that there is a remarkable improvement with decreasing device dimensions. The overall gate length (L), work functions of gate materials, oxide thickness (tox), silicon thickness (tsi) and doping concentration (Nd) are optimized at 60nm, 4.8eV, 4.6eV, 4.4eV, 1nm, 10nm and 1019 cm-3 respectively. The 2-D Poisson equation has been solved by using parabolic approximation technique to obtain the potential distribution function in the channel. Based on this expression, analytical models of the lateral electric field, subthreshold slope and drain current for Junctionless Triple Material Double Gate Metal oxide semiconductor Field Effect Transistor (JL TMDG MOSFET) were derived. Finally, the validity of the proposed analytical model is compared with numerical solution simulation data results which are obtained by using TCAD device simulator.

A TCAD device simulator for exotic materials and its application to a negative-capacitance FET

A new device simulator named Impulse TCAD was developed, being built on top of a nonlinear finite volume method solver, which is further based on the Python script language and its associated scientific libraries. The user can fully customize the device properties and/or equations using scripts, which allows ready handling of exotic materials with nonstandard physical models. As a demonstration, a transient analysis of a negative-capacitance field-effect transistor (NC FET) is presented. The ferroelectric material in the NC FET is handled by using the time-dependent Ginzburg–Landau–Devonshire (GLD) equation, while standard device equations are applied for the rest of the device. The simulations show that, starting from the spontaneous polarization state, the ferroelectric regions evolve into the negative-capacitance regime, showing the expected characteristics of a NC FET. They also indicate that the Ginzburg term in the GLD equation, which is related to the correlation radius $$r_{\mathrm{c}}$$ , plays an important role in the appearance of the negative-capacitance effect. When $$r_{\mathrm{c}}$$ is too short compared with the channel length, the ferroelectric region becomes segregated into multiple polarization domains, resulting in loss of the NC FET characteristic.

Performance enhancement of a proposed solar cell microstructure based on heavily doped silicon wafers

This paper aims to present a proposed npn solar cell microstructure based on low cost heavily doped Silicon wafers. The physical perception of the proposed structure is based on the idea of vertical generation and lateral collection of light generated carriers. It should be mentioned that our structure can be utilized whenever the diffusion length of photogenerated electron hole pairs is smaller than the penetration depth of the solar radiation. The enhancement in the structure performance is attained by the optimization of the structure technological and geometrical parameters and based on practical considerations. This enhancement enables achieving the maximum possible structure conversion efficiency. Moreover, the optical performance, in terms of the spectral response and external quantum efficiency, is presented. The optimization is carried out using SILVACO TCAD process and device simulators. The main parameters used in optimization include the thickness and doping of the top n + layer as well as the sidewall emitter. Additionally, the structure base width along with the notch depth are considered. Finally, back surface treatment is introduced. The structure conversion efficiency in the initial step before optimization was 10.7%. As a result of the optimization process, the structure conversion efficiency is improved to about 15% above the initial case study by 4%.

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.

Electrical Characteristics of Ge/Si-Based Source Pocket Tunnel Field-Effect Transistors.

Two types of Ge/Si-based novel tunnel field-effect transistors (TFETs) with source pockets are proposed. In the proposed Ge/Si-based TFETs, the materials in the source, channel, and drain are Ge, Si, and Si, respectively, and the gate shortly overlaps the source. One of the proposed TFETs has an intrinsic Ge pocket and the other has an intrinsic Si pocket, shallowly doped in the source region below the source-overlapped gate. The current-voltage (I-V) characteristics of the proposed Ge/Si-based TFETs were simulated using the TCAD device simulator, and were compared with those of Si, Ge, and Ge (in source)/Si (in channel and drain) TFETs. The on-currents (ION) of the proposed Ge/Si-based TFETs and Ge-TFET were higher, but the subthreshold swing (SS) of the Ge/Si-based TFET with the Ge source pocket was the worst, owing to the hump effect. The off-current (IOFF) of the Ge-based TFET was the worst, but those of the other devices were the same because their drain material was Si, with a larger band gap than Ge. The SS of the proposed Ge/Si-based TFET with a Si source pocket was the best, because the tunneling length of the Ge/Si heterojunction was the shortest, as shown by the simulated energy band. Defect-induce degradation due to large lattice mismatch between Si and Ge materials is investigated including the trap-assisted-tunneling (TAT) model. Overall, the proposed Ge/Si-based TFET with a Si source pocket demonstrated the best performance.

Analysis of surface radiation damage effects at HL-LHC fluences: Comparison of different technology options

Radiation damage effects at High Luminosity LHC (HL-LHC) fluences greater than 2.2×1016n∕cm2 1 MeV equivalent and total ionizing doses (TID) greater than 1 Grad will impose very stringent constraints in terms of radiation resistance of solid-state detectors. To cope with this design challenge, TCAD tools can be used to study different technology and design options, in order to optimize the performance of silicon detectors in terms of inter-electrode isolation and charge collection properties. A comprehensive modeling approach based on combined bulk and surface damage effects accounting for a limited number of measurable parameters needs therefore to be developed and validated over different technology options. In this work, we mainly focus on the effects of surface damage on detectors fabricated on p-type substrates by different providers. Actually, starting from standard test structure measurements (i.e. MOS capacitors, gated diodes), the integrated interface trap state density (NIT) and the oxide charge (QOX) can be extracted for different vendors and used as input parameter to the simulation tools. Test structures under study include MOS capacitors, gated-diodes, fabricated both at Hamamatsu Photonics (Japan) and at Infineon (Austria). Using High-Frequency (HF) and Quasi-Static (QS) C–V characteristics and current–voltage (I–V) measurements, the effective oxide charge density (NEFF), the surface generation velocity (s0) and the interface trap density (DIT) have been determined and compared for the two technologies before and after irradiation with X-rays with doses ranging from 0.05 to 20 Mrad(SiO2). A detailed simulation analysis on MOS capacitor capacitances and gated diode currents has been carried out, varying the previously mentioned parameters, with the aim to evaluate the effects of oxide charge density and interface trap density increase with the dose. The separate effects of different types of interface trap states have been considered as well, by varying one by one the total density of donor- and acceptor-type trap states, respectively. The effects of different trap energy distributions and capture cross sections have been evaluated within Synopsys Sentaurus TCAD device simulator by means of steady-state, AC and transient analyses. The good agreement obtained for both vendors would support the use of the model as a predictive tool to optimize the design and the operation of novel solid-state detectors in the HL-LHC scenario.