Abstract

The withstand capability and threshold voltage ( $V_{\mathrm {TH}}$ ) instability of 1.2-kV silicon carbide (SiC) MOSFETs under repetitive short circuit (SC) tests are investigated. An SC test system is constructed to apply repetitive SC stress to SiC MOSFETs and measure the transfer $I$ – $V$ characteristics and gate-to-source leakage current ( $I_{\mathrm {GSS}}$ ) after each set of SC tests. To evaluate the SC capability, repetitive SC tests with different SC durations ( $t_{p}$ ) are conducted until device failure. The SC withstand time (SCWT) at 1000 SC cycles is found to be $\sim 3.3~\mu \text{s}$ . $V_{\mathrm {TH}}$ instability under repetitive SC tests prior to the device failure is characterized. A bidirectional $V_{\mathrm {TH}}$ shift behavior, i.e., negative shift at shorter $t_{p}$ and positive shift at longer $t_{p}$ , was revealed. The $V_{\mathrm {TH}}$ shifts under repetitive SC tests are attributed to the SC pulse process according to the results of high-temperature reverse bias (HTRB) and dynamic high-temperature gate bias (HTGB) tests. The underlying mechanisms of the complex $V_{\mathrm {TH}}$ shift behavior are explained in a unified framework by taking into account the junction temperature ( $T_{j}$ ) increase with longer $t_{p}$ . TCAD device simulation is used to help analyze the mechanisms.

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