Taiwan Semiconductor Manufacturing Company Research Articles

An on-chip soft-start pseudo-current hysteresis-controlled buck converter for automotive applications

This paper introduces a novel direct current to direct current (DC-DC) buck converter that uses a pseudo-current hysteresis controller and an on-chip soft start circuit for improved transient performance in automotive applications. The proposed converter, implemented with Taiwan semiconductor manufacturing company (TSMC) 0.18 µm complementary metal oxide semiconductor (CMOS) one-poly-six-metal (1P6M) technology, includes a rail-to-rail current detection circuit and an on-chip soft start circuit to handle transient responses and improve efficiency. Transient response analysis shows fast settling times of 28 µs for both load current changes from 100 mA to 1 A and reversals with consistent transient voltages of approximately 190 mV and peak power efficiency of 99.32% at 5 V output voltage and 100 mA load current. Additionally, the converter maintains a constant output voltage of approximately 5 V across the entire load current range with an average accuracy of 90.41%. A comparative analysis with previous work shows superior performance in terms of figure of merit (FOM). Overall, the proposed pseudo-current hysteresis controlled buck converter exhibits remarkable transient response, load regulation and power efficiency, positioning it as a promising solution for demanding applications, particularly in automotive systems where precise voltage regulation is crucial.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP.

An improved transient performance boost converter using pseudo-current hysteresis control

This paper introduces an enhanced low transient voltage and fast transient response boost converter. It uses a hysteresis-controlled circuit fed by a voltage signal from a rail-to-rail current sensor, resulting in improved efficiency, and transient response. The converter is designed using Taiwan semiconductor manufacturing company (TSMC) 0.18 µm CMOS 1P6M technology, delivers an output voltage of 1.8 V while operating with an input voltage range of 0.5 V to 1 V and supports an output load current range of 10 to 100 mA. The key contributions of this paper are: i) introducing a new boost converter architecture employing pseudo-current hysteresis-controlled (PCHC) techniques, ii) incorporating voltage and current loops into the proposed architecture, and iii) demonstrating superior transient performance. Experimental measurements reveal a peak power efficiency of 98.6% at 10 mA and transient times of 15.4 µs and 11.8 µs for a step load change from 10 to 100 mA and back to 10 mA, respectively, with transient voltages of 51 mV. The presented boost converter outperforms in terms of performance, compared to previous works using the figure of merit (FOM) formula.

Area‐ and energy‐efficient high‐throughput QC‐LDPC encoder for space applications

AbstractAn area‐ and energy‐efficient encoding method and encoder architecture are proposed for the quasi‐cyclic low‐density parity check (LDPC) in near‐earth applications recommended by the Consultant Committee for Space Data Systems. The proposed encoding method reduces the computational complexity using a switch network before bit XOR operations in vector–matrix multiplication. A fully parallel LDPC encoder is implemented on the Taiwan Semiconductor Manufacturing Company 90 nm complementary metal oxide semiconductor (CMOS) technology, achieving a throughput of 10.06 Tbps with the lower area and energy utilization.

The Metaphysics of Globalization in Gadamer: A Case Study of Contemporary Taiwan

This manuscript introduces Gadamer’s metaphysical concept of fusion of horizons as a key to solving the conflicts arising in global capital, cultural, and religious issues. The globalization of contemporary Taiwan is discussed as a case study that covers three aspects: capital, cultural, and religious. TSMC (Taiwan Semiconductor Manufacturing Company), war tension across the Taiwan Strait, and local evangelism are explored separately to illustrate the present scenario of Taiwan’s globalization. In conclusion, the author calls for a fusion of horizons in solving capital interest conflicts, international political tension, and diverse religious beliefs.

ASIC design of LZ77 compressor for computational storage drives

AbstractThe advent of cloud computing, 5G, and artificial intelligence technology has spurred the exponential growth of big data and the need for data compression. To alleviate the CPU burden, computational engines for data compression integrated into network cards and storage devices, giving rise to computational storage. However, computational storage faces several challenges, such as limited memory resources for large hash tables, data dependency for parallel encoding and decoding, and stringent requirements for bandwidth, latency, and power efficiency. Here, an application‐specific integrated circuit‐based LZ77 solution that aims to address these challenges is proposed. Our solution reduces the hash table resource consumption and the bandwidth fluctuations, while achieving high compression ratios. The solution is implemented using Taiwan Semiconductor Manufacturing Company Limited 12 nm technology and demonstrate that a single LZ77 engine can achieve a 4 GB/s throughput at 1 GHz clock frequency. By using four engines, a computational storage drive to achieve 16 GB/s compression bandwidth is enabled. The solution achieves a comparable compression ratio as the standard LZ77 algorithm with a negligible compression ratio loss of 5%, balancing efficiency and effectiveness.

A 0.45‐V low‐power low‐noise amplifier using a wideband image‐rejection technology

AbstractA 0.45‐V low‐power wideband image‐rejection low‐noise amplifier (LNA) using Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS process has been proposed. The supply voltage, power consumption and chip area of the proposed LNA can be reduced using forward body biasing, folded cascode topology and a feedback capacitor. Moreover, a wideband gain‐enhancement‐and‐image‐rejection (WGEIR) circuit including a variable resonant LC tank and a common‐gate amplifier has been developed. The inductance of the variable resonant LC tank can enlarge the gain of the proposed LNA. The capacitance of the variable resonant LC tank can achieve the image rejection. Using the WGEIR circuit, gain enhancement and wideband image rejection can be achieved simultaneously. The variable inductors and capacitors are developed for suppressing wideband image signals and good image rejection ratio (IRR). The combination of the variable inductors and capacitors can achieve eight image‐reject frequencies under three control voltages. The proposed LNA shows the measured results including a 10‐dB power gain, a 3‐dB noise figure (NF) and a −11‐dBm input third‐order intercept point (IIP3) at 2.4 GHz, respectively. The measured IRR ranges from 18 to 23 dBc around 3.6–4.5 GHz, which is 900‐MHz image‐reject bandwidth. The measured proposed LNA using the mentioned techniques consumes 0.8‐mW power.

Dynamic capabilities and asset orchestration

AbstractIn recent years, the theory of dynamic capabilities (DC) has become more sophisticated and has become a framework for sustainable growth through strategic innovation in companies. The “asset orchestration” function, a core concept of DC, connects various types of knowledge (assets) in an entrepreneurial manner and realizes the recombination, modification, and transformation of existing knowledge (assets) for the purpose of developing new businesses, new products, and so forth. However, the dynamic mechanism of such asset orchestration is largely unclarified in previous studies. This paper derives a dynamic theoretical model of asset orchestration and the components of DC necessary for companies to respond to the uncertainty of business environments and the speed of environmental change. Using the findings of the derived theoretical model, this paper analyzes in‐depth case studies of Taiwan Semiconductor Manufacturing Company, which is currently attracting worldwide attention as a core company in the semiconductor industry, to verify the validity of the theoretical model.

A 4–5.2 GHz PLL with 74.8 fs RMS jitter in 28 nm for RF Sampling Transceiver application

AbstractThis paper presents a novel ultra low jitter phase‐locked loop (PLL) circuit architecture for RF Sampling Transceiver. The programmable frequency divider with duty cycle expansion and the new phase frequency detector and charge pump circuit are used to solve the problem of voltage domain conversion of narrow pulses in the traditional high‐performance charge pump PLL structure. The traditional structure degrades charge pump linearity and noise, thus deteriorating overall jitter performance. Furthermore, voltage‐controlled oscillator uses the dual core structure and the second harmonic suppression technology, combined with the proposed new switching capacitor structure, and achieves −139.3 dBc/Hz phase noise at the 1 MHz frequency offset of the 5.2 GHz carrier under the open loop state. The PLL implemented in a standard Taiwan Semiconductor Manufacturing Company 28 nm process occupies a core area of 0.4 mm2 and generates a frequency ranging from 4 to 5.2 GHz using 50 MHz oscillator input, the power consumption is 40 mW. It achieves 74.8 fs root‐mean‐square jitter integrated from 10 KHz to 30 MHz. When the PLL output is divided by 2, the output phase noise at 1 MHz frequency offset is −125.75 dBc/Hz, and the PLL FoM is −246.

Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder

For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder, decoding performance and area efficiency must be balanced. This paper adopts a layered decoder method to improve the area efficiency of the decoder. By parallel processing of three submatrices and storage reuse of node information, optimizing the matrix partitioning and processing order of the 50G-PON standard, the throughput of 1235 bps was reached under 100 MHz circuit frequency in field-programmable gate array (FPGA) implementation, and 9.864 Gbps was achieved based on Taiwan semiconductor manufacturing company (TSMC) 65 nm synthesis with 800 MHz circuit frequency in an area of 2.61 mm2 by proposing a mechanism of spare decision storage to avoid errors caused by quantization overflow of the decoder and using full verification to terminate decoding in advance to improve performance. Finally, at an input bit error rate (BER) of 2.3×10−2 (signal-to-noise ratio (SNR) of about 3.72 dB), the output BER was lower than 10−12, and the throughput area rate (TAR) also increased by 2 to 4 times compared with other papers. In conclusion, an area-efficient LDPC decoder without sacrificing decoding performance is made.

Adaptive STDP-based on-chip spike pattern detection.

A spiking neural network (SNN) is a bottom-up tool used to describe information processing in brain microcircuits. It is becoming a crucial neuromorphic computational model. Spike-timing-dependent plasticity (STDP) is an unsupervised brain-like learning rule implemented in many SNNs and neuromorphic chips. However, a significant performance gap exists between ideal model simulation and neuromorphic implementation. The performance of STDP learning in neuromorphic chips deteriorates because the resolution of synaptic efficacy in such chips is generally restricted to 6 bits or less, whereas simulations employ the entire 64-bit floating-point precision available on digital computers. Previously, we introduced a bio-inspired learning rule named adaptive STDP and demonstrated via numerical simulation that adaptive STDP (using only 4-bit fixed-point synaptic efficacy) performs similarly to STDP learning (using 64-bit floating-point precision) in a noisy spike pattern detection model. Herein, we present the experimental results demonstrating the performance of adaptive STDP learning. To the best of our knowledge, this is the first study that demonstrates unsupervised noisy spatiotemporal spike pattern detection to perform well and maintain the simulation performance on a mixed-signal CMOS neuromorphic chip with low-resolution synaptic efficacy. The chip was designed in Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm CMOS technology node and comprises a soma circuit and 256 synapse circuits along with their learning circuitry.

An Efficient Hardware Implementation for Complex Square Root Calculation Using a PWL Method

In this paper, we propose a methodology for computing the square root of a complex number based on a piecewise linear (PWL) approximation method. The proposed method relies on a software-based segmentor that automatically divides the three real square root functions used in complex square root computation into the fewest segments with a predefined fractional bit width and maximum absolute error (MAE). The coefficients, including the start point, end point, slope and y-intercept of each segment, are stored for use in the implementation of the hardware design. The proposed fully pipelined circuit is coded in the Verilog hardware description language (HDL). The results of synthesis in TSMC (Taiwan Semiconductor Manufacturing Company) 65-nm CMOS technology show that our design achieves savings of 64.21% in area, 16.67% in delay and 65.08% in power compared to the existing methods. Moreover, implementation results on an FPGA (Field-Programmable Gate Array) platform (XC7Z020-CLG400) show that the proposed design reduces the number of LUTs by 29.38%, delay by 28.57% and power consumption by 53.47%.

Shifted paradigm in technonationalism in the 21st century: The influence of global value chain (GVC) and US-China competition on international politics and global commerce —A case study of Japan's semiconductor industry

Because of escalating technological conflicts, the US-China technology war, and hegemonic competition since the late 2010s, “technonationalism,” has become a critical topic in the international political economy, and this study contributes to the ongoing discussion proposing two mediating variables, the global value chain (GVC) and the US-China competition in the 2010s. First, we propose a shift in the technonationalist paradigm, from focusing on a single-state approach with an industrial policy oriented toward development to a multistate focus approach with a geoeconomic strategy oriented toward security. It also highlights the integration of business interests into the national strategic agenda as a critical criterion. Second, the study examines investment in Japan by Elpida Memory, Kioxia, and Taiwan Semiconductor Manufacturing Company. Based on Japan as a case study, the findings show a shift to technonationalism, as the government responds to changes in international political conditions, rather than to domestic demands for supporting a specific segment of the semiconductor industry.

VDIBA-Based Current-Mode PID Controller Design

This paper aims to bring a voltage differencing inverting buffered amplifier (VDIBA)-based current-mode (CM) proportional integral derivative (PID) controller circuit. This CM PID controller is designed with a single VDIBA, three resistors, and two grounded capacitors. The proposed circuit is easy to design, and the control parameters can be tuned without changing the design configuration. A sensitivity analysis of the control parameters to electronic components has been conducted. The Simulation Program with Integrated Circuit Emphasis (SPICE) simulation has been performed using Taiwan Semiconductor Manufacturing Company (TSMC) [Formula: see text]m complementary metal-oxide semiconductor (CMOS) technology parameters. An application circuit example is given to demonstrate the reliability of the proposed PID design. A comparison table of the PID controllers previously reported in the literature is also presented.

A Wirelessly Powered System of Coherent Sensing Nodes for Fracture Mapping Applications at Temperatures up to 250 °C and Pressures up to 24 MPa

Fracture mapping is essential in hydraulic fracturing and finds applications in the oil and gas industry. Mapping of fractures using traditional radioactive or microseismic methods involves contamination and is prone to being inaccurate, thereby reducing the yield in fracturing applications. Therefore, wireless sensor networks (WSNs) with each sensing node having a small form factor and low power consumption are currently being investigated for use in such applications. This paper presents a fully battery-less system of coherent sensing nodes using wireless energy harvesting. These nodes are capable of mapping fractures reliably at temperatures up to 250 °C and pressures up to 24 MPa. Each node comprises a microchip having dimensions of 1.1 mm X 0.56 mm, two coils of 8 mm diameter each, and resonating capacitors. The microchip was fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm process. The node receives a 40.68 MHz radio frequency (RF) signal in the industrial, scientific, and medical applications (ISM) band and transmits back a locked sub-harmonic 13.56 MHz ISM band RF signal. The sub-harmonic signal is generated on-chip using a digital divide-by-3 circuit, drastically reducing the microchip power consumption compared to injection-locked oscillators or phase-locked loops (PLLs). The sensor nodes used in the system have a form factor of 17 mm X 12 mm X 0.2 mm and a minimum average power consumption of 1.5 μW.

Design and Measurement of Microelectromechanical Three-Axis Magnetic Field Sensors Based on the CMOS Technique.

The design, fabrication, and measurement of a microelectromechanical system (MEMS) three-axis magnetic field sensor (MFS) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The MFS is a magnetic transistor type. The performance of the MFS was analyzed employing the semiconductor simulation software, Sentaurus TCAD. In order to decrease the cross-sensitivity of the three-axis MFS, the structure of the MFS is planed to accommodate two independent sensing components, a z-MFS utilized to sense magnetic field (M-F) in the z-direction and a y/x-MFS composed of a y-MFS and a x-MFS to be utilized to sense M-F in the y- and x-directions. The z-MFS incorporates four additional collectors to increase its sensitivity. The commercial 1P6M 0.18 μm CMOS process of the Taiwan Semiconductor Manufacturing Company (TSMC) is utilized to manufacture the MFS. Experiments depict that the MFS has a low cross-sensitivity of less than 3%. The sensitivities of z-, y-, and x-MFS are 237 mV/T, 485 mV/T, and 484 mV/T, respectively.

Area, Delay, and Energy-Efficient Full Dadda Multiplier

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware implementation. In this paper, a modified-Dadda algorithm-based multiplier is designed using a proposed half-adder-based carry-select adder with a binary to excess-1 converter and an improved ripple-carry adder (RCA). The proposed design is simulated in different technologies, i.e., Taiwan Semiconductor Manufacturing Company (TSMC) 50[Formula: see text]nm, 90[Formula: see text]nm, and 120[Formula: see text]nm, and on different GHz frequencies, i.e., 0.5, 1, 2, and 3.33[Formula: see text]GHz. Specifically, the 4-bit circuit of the proposed design in TSMC’s 50[Formula: see text]nm technology consumes 25[Formula: see text]uW of power at 3.33[Formula: see text]GHz with 76[Formula: see text]ps of delay. The simulation results reveal that the design is faster, more power-energy-efficient, and requires a smaller number of transistors for implementation as compared to some closely related works. The proposed design can be a promising candidate for low-power and low-cost digital controllers. In the end, the design has been compared with recent relevant works in the literature.

An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation

Among expectation propagation (EP)-based massive multiple-input–multiple-output (MIMO) detection algorithms, EP with weighted Neumann-series approximation (EPA-wNSA) has the lowest computational complexity while requiring many iterations to guarantee the detection performance, which severely limits the throughput of hardware implementations. Through the joint optimization of algorithm and hardware architecture, we propose an EP-based detector with higher throughput and area efficiency. First, the second-order Richardson iteration (SORI) algorithm is employed to replace the wNSA algorithm for higher convergence speed. Then three algorithmic transformations are proposed to minimize the overall complexity. Simulation results show that the proposed EPA-SORI algorithm requires much fewer iterations to achieve comparable or even better detection performance compared with EPA-wNSA. Furthermore, an efficient detector architecture is delicately designed by incorporating multiple optimization methods, such as reverse data flow, advanced addition, and rounding cells. Implemented with the Taiwan Semiconductor Manufacturing Company (TSMC) 28-nm CMOS technology, the proposed detector has <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> higher throughput than the state-of-the-art EP-based detector.

Stock Prediction of TSMC and Intel using Machine Learning

The advancement of communications, computers, healthcare, military systems, transportation, renewable energy, and numerous more uses is made possible by semiconductors, which are a crucial part of electronic equipment. Semiconductors have been experiencing a shortage due to various reasons. Thus, the increasing demand for chips has attracted countless people to invest in the semiconductor industry. Intel Corporation and Taiwan Semiconductor Manufacturing Company Limited (TSMC) are two companies that can be said to be dominating the industry currently as they have been making very advanced chips. As two giant suppliers in the semiconductor industry, they are close substitutes and competitors. This essay is going to evaluate Intel and TSMC s’ stocks for investors by using the method of machine learning to estimate and predict the future trend of the two stocks. The two models that will be used in the essay are the Linear model and the Long Short-Term Memory model (LSTM), showing the outcome of prediction and determining which stock is better for the investment.