Efficient Layered Parallel Architecture and Application for Large Matrix LDPC Decoder

Abstract

For a 50G passive optical network (PON) low-density parity-check (LDPC) decoder, decoding performance and area efficiency must be balanced. This paper adopts a layered decoder method to improve the area efficiency of the decoder. By parallel processing of three submatrices and storage reuse of node information, optimizing the matrix partitioning and processing order of the 50G-PON standard, the throughput of 1235 bps was reached under 100 MHz circuit frequency in field-programmable gate array (FPGA) implementation, and 9.864 Gbps was achieved based on Taiwan semiconductor manufacturing company (TSMC) 65 nm synthesis with 800 MHz circuit frequency in an area of 2.61 mm2 by proposing a mechanism of spare decision storage to avoid errors caused by quantization overflow of the decoder and using full verification to terminate decoding in advance to improve performance. Finally, at an input bit error rate (BER) of 2.3×10−2 (signal-to-noise ratio (SNR) of about 3.72 dB), the output BER was lower than 10−12, and the throughput area rate (TAR) also increased by 2 to 4 times compared with other papers. In conclusion, an area-efficient LDPC decoder without sacrificing decoding performance is made.