64-QAM調變/解調變之通道解碼系統整合設計與實作

Abstract

In this thesis, the design and implement of system integration for modulation, demodulation and channel decoding architectures is presented. It includes four parts, design of the additive white Gaussian noise (AWGN) generator, design of the 64-QAM modulator and demodulator, design of the low density parity check (LDPC) decoder, and system integration. The AWGN generator circuit was designed based on the algorithm proposed by Wallace. The Gaussian random number generator combines the uniform random numbers with the Gaussian random number distribution. However, the standard deviation of this Gaussian random numbers is one. These numbers need to be multiplied by the parameter related to the signal to noise ratio (SNR) to become the actual AWGN to be added to the modulated signals. The maximum log likelihood approximation was used to generate the approximated log likelihood ratios (LLR) by dividing the mapping relations to several segments. That facilitates hardware implementation by using adders and shifters. With the appropriate selection of fixed points and adjustable parameters, the LDPC decoder can achieve the optimized performance. For the channel decoding, the quasi-cyclic LDPC (QC-LDPC) decoder was adopted. Owing to the limitation of routing complexity of FPGA chips, massive parallel computation of LDPC decoding was reduced by extending the computation time in order to reduce the routing complexity and let FPGA complete the routing process. Finally, the above circuits were integrated for fast evaluating the performance of LDPC decoders. Firstly, the system excesses the input codeword from the FPGA chip internally. Then, the massive decoding processes are performed after the noises are added. If the decoded data are not correct, an error number accumulation circuit counts the errors automatically. The computer only sends the starting message to FPGA, so the limitation of slow data transferring between computer and FPGA are no longer exists. This system was verified using Virtex5 XCVLX330. When the system runs at the clock frequency of 48MHz provided by the interface of Verilink, the throughput reaches 192Mbps. The run time is only one second when the BER is 10-5. Even for the BER of 10-10, one and a half days will be enough. With this system, the analysis speed to evaluate decoding performance is enhanced significantly.