Designing and implementing Low Density Parity Check (LDPC) Decoders using FPGAs

Abstract

Low Density Parity Check (LDPC) Codes offer remarkable error correction performance and therefore increase the design space for communication systems. When implementation complexity and latency are not system limitations, LDPC codes can offer near Shannon Limit performance by using large code lengths and increasing the number of iterations in the decoding process. Furthermore, LDPC codes with smaller block sizes are also of value to the communications system designer and LDPC codes have found practical use in DVB-S2 and other standards. This paper considers design issues with respect to FPGA implementation of LDPC Decoders. Specifically, this paper presents a scalable FPGA architecture for LDPC soft decision decoding based on the Sum Product Algorithm (SPA) for regular LDPC codes. The paper begins with an overall discussion of issues surrounding the use of LDPC codes, followed by a discussion of LDPC decoding using the SPA. A scalable FPGA implementation of an SPA LDPC Decoder is introduced. Design data is provided to support FPGA implementation of this approach for LDPC decoding and quantify required hardware resources. A discussion of trade space for LDPC code implementation based on the FPGA resources is also provided. Finally, an example design is provided based on a Xilinx Virtex-7 to illustrate the concepts discussed in the paper and provide insight into the challenging task of implementing an LDPC decoder in FPGAs.